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Angel Pons60ec3652020-04-03 01:22:13 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Barnali Sarkar2ed14f62016-11-29 16:51:08 +05302
3#ifndef _GPIORVP7_H
4#define _GPIORVP7_H
5
6#include <soc/gpe.h>
7#include <soc/gpio.h>
8
9/* TCA6424A I/O Expander */
10#define IO_EXPANDER_BUS 4
11#define IO_EXPANDER_0_ADDR 0x22
12#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */
13#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */
14#define IO_EXPANDER_P1CONF 0x0D
15#define IO_EXPANDER_P1DOUT 0x05
16#define IO_EXPANDER_P2CONF 0x0E
17#define IO_EXPANDER_P2DOUT 0x06
18#define IO_EXPANDER_1_ADDR 0x23
19
20
21/* GPE_EC_WAKE */
22#define GPE_EC_WAKE GPE0_LAN_WAK
23
24/* CHROMEEC in RVP */
25#define EC_SCI_GPI GPP_E16
26#define EC_SMI_GPI GPP_E15
27/*
28 * Gpio based irq for touchpad, 18th index in North Bank
29 * MAX_DIRECT_IRQ + GPSW_SIZE + 19
30 */
31#define KBLRVP_TOUCHPAD_IRQ 33
32
33#define KBLRVP_TOUCH_IRQ 31
34
35#define BOARD_TOUCHPAD_NAME "touchpad"
36#define BOARD_TOUCHPAD_IRQ KBLRVP_TOUCHPAD_IRQ
37#define BOARD_TOUCHPAD_I2C_BUS 0
38#define BOARD_TOUCHPAD_I2C_ADDR 0x20
39
40#define BOARD_TOUCHSCREEN_NAME "touchscreen"
41#define BOARD_TOUCHSCREEN_IRQ KBLRVP_TOUCH_IRQ
42#define BOARD_TOUCHSCREEN_I2C_BUS 0
43#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c
44
45#ifndef __ACPI__
46
47/* Pad configuration in ramstage. */
48static const struct pad_config gpio_table[] = {
49/* PM_SLP_S0ix_R_N*/ PAD_CFG_GPO(GPP_A7, 1, DEEP),
50/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
51/* PCH_CLK_PCI_TPM */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
52/* PCH_LPC_CLK */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP),
53/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 1, RSMRST),
54/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
55/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
56/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
57/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
58/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
59/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
60/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
61/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
62/* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP),
63/* ISH_GP5 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP),
64/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
65/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
66/* HSJ_MIC_DET */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
67/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
68/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP),
69/* SRCCLKREQ0# */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP),
70/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
71/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
72/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
73/* GPP_B_14_SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP),
74/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, PLTRST, YES),
75/* TBT_CIO_PLUG_EVT */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PU, PLTRST, YES),
76/* PCH_SLOT1_WAKE_N */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, PLTRST, YES),
77/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
78/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1),
79/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1),
80/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
81/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP),
82/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
83/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
84/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP),
85/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
86/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
87/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, DEEP),
88/* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
89/* USB_CTL */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1),
90/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
91/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
92/* NFC_RST* */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
93/* EN_PP3300_KEPLER */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
94/* PCH_MEM_CFG0 */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
95/* PCH_MEM_CFG1 */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
96/* PCH_MEM_CFG2 */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
97/* PCH_MEM_CFG3 */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
98/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
99/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
100/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
101/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
102/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
103/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
104/* TCH_PNL_PWREN */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
105/* SPI_WP_STATUS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
106/* ITCH_SPI_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
107/* ITCH_SPI_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
108/* ITCH_SPI_MISO_1 */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
109/* ITCH_SPI_MISO_0 */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
110/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
111/* EN_PP3300_DX_EMMC */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
112/* EN_PP1800_DX_EMMC */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
113/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
114/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
Furquan Shaikh219ebb92017-10-06 17:05:50 -0700115 PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, DEEP),
116/* SD_D3_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP),
117/* USB_A1_ILIM_SEL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP),
118/* EN_PP3300_DX_CAM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP),
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530119/* EN_PP1800_DX_AUDIO */PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
120/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
121/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
122/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
123/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
124/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1),
125/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
126/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1),
127/* ITCH_SPI_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
128/* ITCH_SPI_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
129/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
130/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, 20K_PD, DEEP),
131/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
Furquan Shaikh219ebb92017-10-06 17:05:50 -0700132/* SSD_PEDET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E2, NONE, DEEP),
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530133/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, RSMRST),
134/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
135/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
136 PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
137/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
138/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
139/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
140/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
141/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
142/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
143/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, YES),
144/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
145/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
146/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
147/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
148/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
149/* PCH_CODEC_IRQ */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
150/* TCH_PNL_RST */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP),
151/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
152/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
153/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
154/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
155/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
156/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
157/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
158/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
159/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
160/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
161/* AUDIO_IRQ */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF2),
162/* I2C5_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF2),
163/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
164/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
165/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
166/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
167/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
168/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
169/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
170/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
171/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
172/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
173/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
174/* WWAN_UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP),
175/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
176/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
177/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
178/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
179/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
180/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
181/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
182/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
183/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
184/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
185/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
186/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
187/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
188/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
189/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
190 PAD_CFG_NF(GPD7, NONE, DEEP, NF1),
191/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
192/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
193/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
194/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
195};
196
197/* Early pad configuration in romstage. */
198static const struct pad_config early_gpio_table[] = {
199/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
200/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
201};
202
203
204#endif
205
206#endif