Patrick Rudolph | 5449007 | 2019-01-16 13:44:33 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> |
| 6 | * Copyright (C) 2017 Gergely Kiss <mail.gery@gmail.com> |
| 7 | * Copyright (C) 2019 9Elements GmbH <patrick.rudolph@9elements.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | */ |
| 19 | |
| 20 | #include <device/device.h> |
| 21 | #include <device/pnp.h> |
Patrick Rudolph | 5449007 | 2019-01-16 13:44:33 +0100 | [diff] [blame] | 22 | #include <superio/conf_mode.h> |
| 23 | |
| 24 | #include "it8528e.h" |
| 25 | |
| 26 | static void it8528e_init(struct device *dev) |
| 27 | { |
| 28 | } |
| 29 | |
| 30 | static struct device_operations ops = { |
| 31 | .read_resources = pnp_read_resources, |
| 32 | .set_resources = pnp_set_resources, |
| 33 | .enable_resources = pnp_enable_resources, |
| 34 | .enable = pnp_alt_enable, |
| 35 | .init = it8528e_init, |
| 36 | .ops_pnp_mode = &pnp_conf_mode_870155_aa, |
| 37 | }; |
| 38 | |
| 39 | static struct pnp_info pnp_dev_info[] = { |
| 40 | { NULL, IT8528E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, |
| 41 | { NULL, IT8528E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, |
| 42 | { NULL, IT8528E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, |
| 43 | { NULL, IT8528E_KBCM, PNP_IRQ0, }, |
| 44 | /* Documentation: Program io0 = 0x60 and io1 = 0x64 */ |
| 45 | { NULL, IT8528E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, |
| 46 | { NULL, IT8528E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, }, |
| 47 | { NULL, IT8528E_SMFI, PNP_IO0 | PNP_IRQ0, 0xfff0, }, |
| 48 | /* Documentation: Program io0 = 0x70 and io1 = 0x272 */ |
| 49 | { NULL, IT8528E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, |
| 50 | 0xfffe, 0xfffe, 0xfffe, 0xfffe}, |
| 51 | /* Documentation: Program io0 = 0x62 and io1 = 0x66 */ |
| 52 | { NULL, IT8528E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, |
| 53 | { NULL, IT8528E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, 0x07fc, |
| 54 | 0x07fc, 0xfff0 }, |
| 55 | /* Documentation is unclear if PMC3-5 have LPC I/O decoding support */ |
| 56 | { NULL, IT8528E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, |
| 57 | { NULL, IT8528E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, |
| 58 | { NULL, IT8528E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, |
| 59 | { NULL, IT8528E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 }, |
| 60 | { NULL, IT8528E_PECI, PNP_IO0, 0xfff8 }, |
| 61 | }; |
| 62 | |
| 63 | static void enable_dev(struct device *dev) |
| 64 | { |
| 65 | pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); |
| 66 | } |
| 67 | |
| 68 | struct chip_operations superio_ite_it8528e_ops = { |
| 69 | CHIP_NAME("ITE IT8528E Super I/O") |
| 70 | .enable_dev = enable_dev, |
| 71 | }; |