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Angel Pons4b429832020-04-02 23:48:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Patrick Georgi2efc8802012-11-06 11:03:53 +01002
3#include <stdint.h>
Patrick Georgi2efc8802012-11-06 11:03:53 +01004#include <device/pci_def.h>
Patrick Georgi2efc8802012-11-06 11:03:53 +01005#include <spd.h>
Patrick Georgi2efc8802012-11-06 11:03:53 +01006
Elyes HAOUASa1e22b82019-03-18 22:49:36 +01007#include "delay.h"
Patrick Georgi2efc8802012-11-06 11:03:53 +01008#include "gm45.h"
9
10void raminit_thermal(const sysinfo_t *sysinfo)
11{
12 const mem_clock_t freq = sysinfo->selected_timings.mem_clock;
13 int x;
14 FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, x) {
15 const chip_width_t width = sysinfo->dimms[x].chip_width;
16 const chip_capacity_t size = sysinfo->dimms[x].chip_capacity;
17 if ((freq == MEM_CLOCK_1067MT) && (width == CHIP_WIDTH_x16)) {
18 MCHBAR32(CxDTPEW(x)) = 0x0d0b0403;
19 MCHBAR32(CxDTPEW(x)+4) = 0x060d;
20 MCHBAR32(CxDTAEW(x)) = 0x2d0b221a;
21 MCHBAR32(CxDTAEW(x)+4) = 0xc779956e;
22 } else
23 if ((freq == MEM_CLOCK_1067MT) && (width == CHIP_WIDTH_x8)) {
24 MCHBAR32(CxDTPEW(x)) = 0x06040101;
25 MCHBAR32(CxDTPEW(x)+4) = 0x0506;
26 if (size == CHIP_CAP_2G)
27 MCHBAR32(CxDTAEW(x)) = 0xa1071416;
28 else
29 MCHBAR32(CxDTAEW(x)) = 0x1a071416;
30 MCHBAR32(CxDTAEW(x)+4) = 0x7246643f;
31 } else
32 if ((freq == MEM_CLOCK_800MT) && (width == CHIP_WIDTH_x16)) {
33 MCHBAR32(CxDTPEW(x)) = 0x06030100;
34 MCHBAR32(CxDTPEW(x)+4) = 0x0506;
35 MCHBAR32(CxDTAEW(x)) = 0x3e081714;
36 MCHBAR32(CxDTAEW(x)+4) = 0xbb79a171;
37 } else
38 if ((freq == MEM_CLOCK_800MT) && (width == CHIP_WIDTH_x8)) {
39 if (size <= CHIP_CAP_512M)
40 MCHBAR32(CxDTPEW(x)) = 0x05050101;
41 else
42 MCHBAR32(CxDTPEW(x)) = 0x05060101;
43 MCHBAR32(CxDTPEW(x)+4) = 0x0503;
44 if (size == CHIP_CAP_2G) {
45 MCHBAR32(CxDTAEW(x)) = 0x57051010;
46 MCHBAR32(CxDTAEW(x)+4) = 0x5fd15dde;
47 } else
48 if (size == CHIP_CAP_1G) {
49 MCHBAR32(CxDTAEW(x)) = 0x3306130e;
50 MCHBAR32(CxDTAEW(x)+4) = 0x5763485d;
51 } else
52 if (size <= CHIP_CAP_512M) {
53 MCHBAR32(CxDTAEW(x)) = 0x1e08170d;
54 MCHBAR32(CxDTAEW(x)+4) = 0x502f3827;
55 }
56 } else
57 if ((freq == MEM_CLOCK_667MT) && (width == CHIP_WIDTH_x16)) {
58 MCHBAR32(CxDTPEW(x)) = 0x02000000;
59 MCHBAR32(CxDTPEW(x)+4) = 0x0402;
60 MCHBAR32(CxDTAEW(x)) = 0x46061111;
61 MCHBAR32(CxDTAEW(x)+4) = 0xb579a772;
62 } else
63 if ((freq == MEM_CLOCK_667MT) && (width == CHIP_WIDTH_x8)) {
64 MCHBAR32(CxDTPEW(x)) = 0x04070101;
65 MCHBAR32(CxDTPEW(x)+4) = 0x0501;
66 if (size == CHIP_CAP_2G) {
67 MCHBAR32(CxDTAEW(x)) = 0x32040e0d;
68 MCHBAR32(CxDTAEW(x)+4) = 0x55ff59ff;
69 } else
70 if (size == CHIP_CAP_1G) {
71 MCHBAR32(CxDTAEW(x)) = 0x3f05120a;
72 MCHBAR32(CxDTAEW(x)+4) = 0x49713a6c;
73 } else
74 if (size <= CHIP_CAP_512M) {
75 MCHBAR32(CxDTAEW(x)) = 0x20081808;
76 MCHBAR32(CxDTAEW(x)+4) = 0x3f23221b;
77 }
78 }
79
80 /* also L-Shaped */
81 if (sysinfo->selected_timings.channel_mode ==
82 CHANNEL_MODE_DUAL_INTERLEAVED) {
83 if (freq == MEM_CLOCK_1067MT) {
84 MCHBAR32(CxGTEW(x)) = 0xc8f81717;
85 } else
86 if (freq == MEM_CLOCK_800MT) {
87 MCHBAR32(CxGTEW(x)) = 0x96ba1717;
88 } else
89 if (freq == MEM_CLOCK_667MT) {
90 MCHBAR32(CxGTEW(x)) = 0x7d9b1717;
91 }
92 } else {
93 if (freq == MEM_CLOCK_1067MT) {
94 MCHBAR32(CxGTEW(x)) = 0x53661717;
95 } else
96 if (freq == MEM_CLOCK_800MT) {
97 MCHBAR32(CxGTEW(x)) = 0x886e1717;
98 } else
99 if (freq == MEM_CLOCK_667MT) {
100 MCHBAR32(CxGTEW(x)) = 0x38621717;
101 }
102 }
103 }
104
105 // always?
106 MCHBAR32(CxDTC(0)) = 0x00004020;
107 MCHBAR32(CxDTC(1)) = 0x00004020;
108 MCHBAR32(CxGTC(0)) = 0x00304848;
109 MCHBAR32(CxGTC(1)) = 0x00304848;
110
111 /* enable thermal sensors */
112 u32 tmp;
113 tmp = MCHBAR32(0x1290) & 0xfff8;
114 MCHBAR32(0x1290) = tmp | 0xa4810007;
115 tmp = MCHBAR32(0x1390) & 0xfff8;
116 MCHBAR32(0x1390) = tmp | 0xa4810007;
117 tmp = MCHBAR32(0x12b4) & 0xfff8;
118 MCHBAR32(0x12b4) = tmp | 0xa2810007;
119 tmp = MCHBAR32(0x13b4) & 0xfff8;
120 MCHBAR32(0x13b4) = tmp | 0xa2810007;
121 MCHBAR8(0x1070) = 1;
122 MCHBAR8(0x1080) = 6;
123 if (sysinfo->gfx_type == GMCH_PM45) {
124 MCHBAR16(0x1001) = 0;
125 MCHBAR8(0x1007) = 0;
126 MCHBAR32(0x1010) = 0;
127 MCHBAR32(0x1014) = 0;
128 MCHBAR8(0x101c) = 0x98;
129 MCHBAR16(0x1041) = 0x9200;
130 MCHBAR8(0x1047) = 0;
131 MCHBAR32(0x1050) = 0x2309;
132 MCHBAR32(0x1054) = 0;
133 MCHBAR8(0x105c) = 0x98;
134 } else {
135 MCHBAR16(0x1001) = 0x9200;
136 MCHBAR8(0x1007) = 0;
137 MCHBAR32(0x1010) = 0x2309;
138 MCHBAR32(0x1014) = 0;
139 MCHBAR8(0x101c) = 0x98;
140 MCHBAR16(0x1041) = 0;
141 MCHBAR8(0x1047) = 0;
142 MCHBAR32(0x1050) = 0;
143 MCHBAR32(0x1054) = 0;
144 MCHBAR8(0x105c) = 0x98;
145 }
146
147 MCHBAR32(0x1010) |= 1 << 31;
148 MCHBAR32(0x1050) |= 1 << 31;
149 MCHBAR32(CxGTC(0)) |= 1 << 31;
150 MCHBAR32(CxGTC(1)) |= 1 << 31;
151
152 if (sysinfo->gs45_low_power_mode) {
153 MCHBAR32(0x11b0) = 0xa000083a;
154 } else if (sysinfo->gfx_type == GMCH_GM49) {
155 MCHBAR32(0x11b0) = 0x2000383a;
156 MCHBAR16(0x1190) &= ~(1 << 15);
157 } else if ((sysinfo->gfx_type != GMCH_PM45) &&
158 (sysinfo->gfx_type != GMCH_UNKNOWN)) {
159 MCHBAR32(0x11b0) = 0xa000383a;
160 }
161
162 switch (sysinfo->selected_timings.fsb_clock) {
163 case FSB_CLOCK_667MHz:
164 MCHBAR32(0x11d0) = 0x0fd88000;
165 break;
166 case FSB_CLOCK_800MHz:
167 MCHBAR32(0x11d0) = 0x1303c000;
168 break;
169 case FSB_CLOCK_1067MHz:
170 MCHBAR32(0x11d0) = 0x194a0000;
171 break;
172 }
173 tmp = MCHBAR32(0x11d4) & ~0x1f;
174 MCHBAR32(0x11d4) = tmp | 4;
175}