Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016-2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <chip.h> |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 17 | #include <compiler.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 18 | #include <console/console.h> |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 19 | #include <device/device.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 20 | #include <device/pci.h> |
| 21 | #include <fsp/api.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 22 | #include <fsp/util.h> |
Subrata Banik | 98376b8 | 2018-05-22 16:18:16 +0530 | [diff] [blame] | 23 | #include <intelblocks/acpi.h> |
Duncan Laurie | 2410cd9 | 2018-03-26 02:25:07 -0700 | [diff] [blame] | 24 | #include <intelblocks/xdci.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 25 | #include <romstage_handoff.h> |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 26 | #include <soc/intel/common/vbt.h> |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 27 | #include <soc/pci_devs.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 28 | #include <soc/ramstage.h> |
| 29 | #include <string.h> |
| 30 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 31 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
Subrata Banik | 98376b8 | 2018-05-22 16:18:16 +0530 | [diff] [blame] | 32 | const char *soc_acpi_name(const struct device *dev) |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 33 | { |
| 34 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 35 | return "PCI0"; |
| 36 | |
| 37 | if (dev->path.type != DEVICE_PATH_PCI) |
| 38 | return NULL; |
| 39 | |
| 40 | switch (dev->path.pci.devfn) { |
| 41 | case SA_DEVFN_ROOT: return "MCHC"; |
| 42 | case SA_DEVFN_IGD: return "GFX0"; |
| 43 | case PCH_DEVFN_ISH: return "ISHB"; |
| 44 | case PCH_DEVFN_XHCI: return "XHCI"; |
| 45 | case PCH_DEVFN_USBOTG: return "XDCI"; |
| 46 | case PCH_DEVFN_THERMAL: return "THRM"; |
| 47 | case PCH_DEVFN_I2C0: return "I2C0"; |
| 48 | case PCH_DEVFN_I2C1: return "I2C1"; |
| 49 | case PCH_DEVFN_I2C2: return "I2C2"; |
| 50 | case PCH_DEVFN_I2C3: return "I2C3"; |
| 51 | case PCH_DEVFN_CSE: return "CSE1"; |
| 52 | case PCH_DEVFN_CSE_2: return "CSE2"; |
| 53 | case PCH_DEVFN_CSE_IDER: return "CSED"; |
| 54 | case PCH_DEVFN_CSE_KT: return "CSKT"; |
| 55 | case PCH_DEVFN_CSE_3: return "CSE3"; |
| 56 | case PCH_DEVFN_SATA: return "SATA"; |
| 57 | case PCH_DEVFN_UART2: return "UAR2"; |
| 58 | case PCH_DEVFN_I2C4: return "I2C4"; |
| 59 | case PCH_DEVFN_I2C5: return "I2C5"; |
| 60 | case PCH_DEVFN_PCIE1: return "RP01"; |
| 61 | case PCH_DEVFN_PCIE2: return "RP02"; |
| 62 | case PCH_DEVFN_PCIE3: return "RP03"; |
| 63 | case PCH_DEVFN_PCIE4: return "RP04"; |
| 64 | case PCH_DEVFN_PCIE5: return "RP05"; |
| 65 | case PCH_DEVFN_PCIE6: return "RP06"; |
| 66 | case PCH_DEVFN_PCIE7: return "RP07"; |
| 67 | case PCH_DEVFN_PCIE8: return "RP08"; |
| 68 | case PCH_DEVFN_PCIE9: return "RP09"; |
| 69 | case PCH_DEVFN_PCIE10: return "RP10"; |
| 70 | case PCH_DEVFN_PCIE11: return "RP11"; |
| 71 | case PCH_DEVFN_PCIE12: return "RP12"; |
Lijian Zhao | 580bc41 | 2017-10-04 13:43:47 -0700 | [diff] [blame] | 72 | case PCH_DEVFN_PCIE13: return "RP13"; |
| 73 | case PCH_DEVFN_PCIE14: return "RP14"; |
| 74 | case PCH_DEVFN_PCIE15: return "RP15"; |
| 75 | case PCH_DEVFN_PCIE16: return "RP16"; |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 76 | case PCH_DEVFN_UART0: return "UAR0"; |
| 77 | case PCH_DEVFN_UART1: return "UAR1"; |
| 78 | case PCH_DEVFN_GSPI0: return "SPI0"; |
| 79 | case PCH_DEVFN_GSPI1: return "SPI1"; |
| 80 | case PCH_DEVFN_GSPI2: return "SPI2"; |
| 81 | case PCH_DEVFN_EMMC: return "EMMC"; |
| 82 | case PCH_DEVFN_SDCARD: return "SDXC"; |
| 83 | case PCH_DEVFN_LPC: return "LPCB"; |
| 84 | case PCH_DEVFN_P2SB: return "P2SB"; |
| 85 | case PCH_DEVFN_PMC: return "PMC_"; |
| 86 | case PCH_DEVFN_HDA: return "HDAS"; |
| 87 | case PCH_DEVFN_SMBUS: return "SBUS"; |
| 88 | case PCH_DEVFN_SPI: return "FSPI"; |
| 89 | case PCH_DEVFN_GBE: return "IGBE"; |
| 90 | case PCH_DEVFN_TRACEHUB:return "THUB"; |
| 91 | } |
| 92 | |
| 93 | return NULL; |
| 94 | } |
| 95 | #endif |
| 96 | |
Lijian Zhao | 0823183 | 2017-09-05 18:16:21 -0700 | [diff] [blame] | 97 | static void parse_devicetree(FSP_S_CONFIG *params) |
| 98 | { |
| 99 | struct device *dev = SA_DEV_ROOT; |
| 100 | if (!dev) { |
| 101 | printk(BIOS_ERR, "Could not find root device\n"); |
| 102 | return; |
| 103 | } |
| 104 | |
| 105 | const config_t *config = dev->chip_info; |
| 106 | const int SerialIoDev[] = { |
| 107 | PCH_DEVFN_I2C0, |
| 108 | PCH_DEVFN_I2C1, |
| 109 | PCH_DEVFN_I2C2, |
| 110 | PCH_DEVFN_I2C3, |
| 111 | PCH_DEVFN_I2C4, |
| 112 | PCH_DEVFN_I2C5, |
| 113 | PCH_DEVFN_GSPI0, |
| 114 | PCH_DEVFN_GSPI1, |
| 115 | PCH_DEVFN_GSPI2, |
| 116 | PCH_DEVFN_UART0, |
| 117 | PCH_DEVFN_UART1, |
| 118 | PCH_DEVFN_UART2 |
| 119 | }; |
| 120 | |
| 121 | for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) { |
| 122 | dev = dev_find_slot(0, SerialIoDev[i]); |
| 123 | if (!dev->enabled) { |
| 124 | params->SerialIoDevMode[i] = PchSerialIoDisabled; |
| 125 | continue; |
| 126 | } |
| 127 | params->SerialIoDevMode[i] = PchSerialIoPci; |
| 128 | if (config->SerialIoDevMode[i] == PchSerialIoAcpi || |
| 129 | config->SerialIoDevMode[i] == PchSerialIoHidden) |
| 130 | params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; |
| 131 | } |
| 132 | } |
| 133 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 134 | void soc_init_pre_device(void *chip_info) |
| 135 | { |
| 136 | /* Perform silicon specific init. */ |
| 137 | fsp_silicon_init(romstage_handoff_is_resume()); |
Subrata Banik | a8733e3 | 2018-01-23 16:40:56 +0530 | [diff] [blame] | 138 | |
| 139 | /* Display FIRMWARE_VERSION_INFO_HOB */ |
| 140 | fsp_display_fvi_version_hob(); |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 141 | } |
| 142 | |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 143 | static void pci_domain_set_resources(device_t dev) |
| 144 | { |
| 145 | assign_resources(dev->link_list); |
| 146 | } |
| 147 | |
| 148 | static struct device_operations pci_domain_ops = { |
| 149 | .read_resources = &pci_domain_read_resources, |
| 150 | .set_resources = &pci_domain_set_resources, |
| 151 | .scan_bus = &pci_domain_scan_bus, |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 152 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
| 153 | .acpi_name = &soc_acpi_name, |
| 154 | #endif |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 155 | }; |
| 156 | |
| 157 | static struct device_operations cpu_bus_ops = { |
| 158 | .read_resources = DEVICE_NOOP, |
| 159 | .set_resources = DEVICE_NOOP, |
| 160 | .enable_resources = DEVICE_NOOP, |
| 161 | .init = DEVICE_NOOP, |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 162 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 163 | }; |
| 164 | |
| 165 | static void soc_enable(device_t dev) |
| 166 | { |
| 167 | /* Set the operations if it is a special bus type */ |
| 168 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 169 | dev->ops = &pci_domain_ops; |
| 170 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 171 | dev->ops = &cpu_bus_ops; |
| 172 | } |
| 173 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 174 | struct chip_operations soc_intel_cannonlake_ops = { |
| 175 | CHIP_NAME("Intel Cannonlake") |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 176 | .enable_dev = &soc_enable, |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 177 | .init = &soc_init_pre_device, |
| 178 | }; |
| 179 | |
| 180 | /* UPD parameters to be initialized before SiliconInit */ |
| 181 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 182 | { |
| 183 | int i; |
| 184 | FSP_S_CONFIG *params = &supd->FspsConfig; |
Lijian Zhao | 91c8e23 | 2018-03-12 18:05:53 -0700 | [diff] [blame] | 185 | FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; |
Duncan Laurie | 2410cd9 | 2018-03-26 02:25:07 -0700 | [diff] [blame] | 186 | struct device *dev = SA_DEV_ROOT; |
Lijian Zhao | 580bc41 | 2017-10-04 13:43:47 -0700 | [diff] [blame] | 187 | config_t *config = dev->chip_info; |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 188 | |
Lijian Zhao | 0823183 | 2017-09-05 18:16:21 -0700 | [diff] [blame] | 189 | /* Parse device tree and enable/disable devices */ |
| 190 | parse_devicetree(params); |
| 191 | |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 192 | /* Load VBT before devicetree-specific config. */ |
Patrick Georgi | 2257959 | 2017-10-06 17:36:09 +0200 | [diff] [blame] | 193 | params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 194 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 195 | /* Set USB OC pin to 0 first */ |
| 196 | for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { |
| 197 | params->Usb2OverCurrentPin[i] = 0; |
| 198 | } |
| 199 | |
| 200 | for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) { |
| 201 | params->Usb3OverCurrentPin[i] = 0; |
| 202 | } |
| 203 | |
| 204 | mainboard_silicon_init_params(params); |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 205 | |
Caveh Jalali | 21df67e | 2018-03-08 17:58:21 -0800 | [diff] [blame] | 206 | /* Unlock upper 8 bytes of RTC RAM */ |
| 207 | params->PchLockDownRtcMemoryLock = 0; |
| 208 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 209 | /* SATA */ |
| 210 | params->SataEnable = config->SataEnable; |
| 211 | params->SataMode = config->SataMode; |
| 212 | params->SataSalpSupport = config->SataSalpSupport; |
| 213 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 214 | sizeof(params->SataPortsEnable)); |
| 215 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 216 | sizeof(params->SataPortsDevSlp)); |
| 217 | |
| 218 | /* Lan */ |
| 219 | params->PchLanEnable = config->PchLanEnable; |
| 220 | |
| 221 | /* Audio */ |
| 222 | params->PchHdaDspEnable = config->PchHdaDspEnable; |
| 223 | params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; |
Lijian Zhao | 416ded8 | 2018-01-23 21:58:36 -0800 | [diff] [blame] | 224 | params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0; |
| 225 | params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1; |
| 226 | params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0; |
| 227 | params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1; |
| 228 | params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2; |
| 229 | params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1; |
| 230 | params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2; |
| 231 | params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3; |
| 232 | params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4; |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 233 | |
Vaibhav Shankar | 2da6ec4 | 2018-03-19 18:56:38 -0700 | [diff] [blame] | 234 | /* S0ix */ |
| 235 | params->PchPmSlpS0Enable = config->s0ix_enable; |
| 236 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 237 | /* USB */ |
| 238 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 239 | params->PortUsb20Enable[i] = |
| 240 | config->usb2_ports[i].enable; |
| 241 | params->Usb2OverCurrentPin[i] = |
| 242 | config->usb2_ports[i].ocpin; |
| 243 | params->Usb2AfePetxiset[i] = |
| 244 | config->usb2_ports[i].pre_emp_bias; |
| 245 | params->Usb2AfeTxiset[i] = |
| 246 | config->usb2_ports[i].tx_bias; |
| 247 | params->Usb2AfePredeemp[i] = |
| 248 | config->usb2_ports[i].tx_emp_enable; |
| 249 | params->Usb2AfePehalfbit[i] = |
| 250 | config->usb2_ports[i].pre_emp_bit; |
| 251 | } |
| 252 | |
| 253 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 254 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 255 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| 256 | if (config->usb3_ports[i].tx_de_emp) { |
| 257 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 258 | params->Usb3HsioTxDeEmph[i] = |
| 259 | config->usb3_ports[i].tx_de_emp; |
| 260 | } |
| 261 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 262 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 263 | params->Usb3HsioTxDownscaleAmp[i] = |
| 264 | config->usb3_ports[i].tx_downscale_amp; |
| 265 | } |
| 266 | } |
| 267 | |
Duncan Laurie | 2410cd9 | 2018-03-26 02:25:07 -0700 | [diff] [blame] | 268 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
| 269 | dev = dev_find_slot(0, PCH_DEVFN_USBOTG); |
| 270 | if (!xdci_can_enable()) |
| 271 | dev->enabled = 0; |
| 272 | params->XdciEnable = dev->enabled; |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 273 | |
Lijian Zhao | 580bc41 | 2017-10-04 13:43:47 -0700 | [diff] [blame] | 274 | /* PCI Express */ |
| 275 | for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { |
| 276 | if (config->PcieClkSrcUsage[i] == 0) |
| 277 | config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; |
| 278 | } |
| 279 | memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, |
| 280 | sizeof(config->PcieClkSrcUsage)); |
| 281 | memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, |
| 282 | sizeof(config->PcieClkSrcClkReq)); |
| 283 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 284 | /* eMMC and SD */ |
| 285 | params->ScsEmmcEnabled = config->ScsEmmcEnabled; |
| 286 | params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; |
Lijian Zhao | 93fde11 | 2018-02-05 18:14:11 -0800 | [diff] [blame] | 287 | params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed; |
| 288 | if (config->EmmcHs400DllNeed == 1) { |
| 289 | params->PchScsEmmcHs400RxStrobeDll1 = |
| 290 | config->EmmcHs400RxStrobeDll1; |
| 291 | params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll; |
| 292 | } |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 293 | params->ScsSdCardEnabled = config->ScsSdCardEnabled; |
| 294 | params->ScsUfsEnabled = config->ScsUfsEnabled; |
| 295 | |
| 296 | params->Heci3Enabled = config->Heci3Enabled; |
| 297 | params->Device4Enable = config->Device4Enable; |
| 298 | params->SkipMpInit = config->FspSkipMpInit; |
| 299 | |
| 300 | /* VrConfig Settings for 5 domains |
| 301 | * 0 = System Agent, 1 = IA Core, 2 = Ring, |
| 302 | * 3 = GT unsliced, 4 = GT sliced */ |
| 303 | for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) |
| 304 | fill_vr_domain_config(params, i, &config->domain_vr_config[i]); |
Lijian Zhao | 91c8e23 | 2018-03-12 18:05:53 -0700 | [diff] [blame] | 305 | |
| 306 | /* Vt-D config */ |
| 307 | tconfig->VtdDisable = config->VtdDisable; |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 308 | } |
| 309 | |
| 310 | /* Mainboard GPIO Configuration */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 311 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 312 | { |
| 313 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 314 | } |