zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pnp.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <device/pci_ops.h> |
| 26 | #include <pc80/mc146818rtc.h> |
| 27 | #include <pc80/isa-dma.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 28 | #include <arch/io.h> |
| 29 | #include "hudson.h" |
| 30 | |
| 31 | static void lpc_init(device_t dev) |
| 32 | { |
| 33 | u8 byte; |
| 34 | u32 dword; |
| 35 | device_t sm_dev; |
| 36 | |
| 37 | /* Enable the LPC Controller */ |
| 38 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 39 | dword = pci_read_config32(sm_dev, 0x64); |
| 40 | dword |= 1 << 20; |
| 41 | pci_write_config32(sm_dev, 0x64, dword); |
| 42 | |
| 43 | /* Initialize isa dma */ |
| 44 | isa_dma_init(); |
| 45 | |
| 46 | /* Enable DMA transaction on the LPC bus */ |
| 47 | byte = pci_read_config8(dev, 0x40); |
| 48 | byte |= (1 << 2); |
| 49 | pci_write_config8(dev, 0x40, byte); |
| 50 | |
| 51 | /* Disable the timeout mechanism on LPC */ |
| 52 | byte = pci_read_config8(dev, 0x48); |
| 53 | byte &= ~(1 << 7); |
| 54 | pci_write_config8(dev, 0x48, byte); |
| 55 | |
| 56 | /* Disable LPC MSI Capability */ |
| 57 | byte = pci_read_config8(dev, 0x78); |
| 58 | byte &= ~(1 << 1); |
| 59 | byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going |
| 60 | on on LPC, it holds PCI grant, so no LPC slave cycle can |
| 61 | interrupt and visit LPC. */ |
| 62 | pci_write_config8(dev, 0x78, byte); |
| 63 | |
| 64 | /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */ |
| 65 | /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ |
| 66 | byte = pci_read_config8(dev, 0xBB); |
| 67 | byte |= 1 << 0 | 1 << 3; |
| 68 | pci_write_config8(dev, 0xBB, byte); |
zbao | ef180e2 | 2012-08-02 19:03:44 +0800 | [diff] [blame] | 69 | |
| 70 | rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | static void hudson_lpc_read_resources(device_t dev) |
| 74 | { |
| 75 | struct resource *res; |
| 76 | |
| 77 | /* Get the normal pci resources of this device */ |
| 78 | pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ |
| 79 | |
| 80 | pci_get_resource(dev, 0xA0); /* SPI ROM base address */ |
| 81 | |
| 82 | /* Add an extra subtractive resource for both memory and I/O. */ |
| 83 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
| 84 | res->base = 0; |
| 85 | res->size = 0x1000; |
| 86 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 87 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 88 | |
| 89 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
| 90 | res->base = 0xff800000; |
| 91 | res->size = 0x00800000; /* 8 MB for flash */ |
| 92 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 93 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 94 | |
| 95 | //res = new_resource(dev, 3); /* IOAPIC */ |
| 96 | //res->base = 0xfec00000; |
| 97 | //res->size = 0x00001000; |
| 98 | //res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 99 | |
| 100 | compact_resources(dev); |
| 101 | } |
| 102 | |
| 103 | static void hudson_lpc_set_resources(struct device *dev) |
| 104 | { |
| 105 | struct resource *res; |
| 106 | |
| 107 | pci_dev_set_resources(dev); |
| 108 | |
| 109 | /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ |
| 110 | res = find_resource(dev, 0xA0); |
| 111 | pci_write_config32(dev, 0xA0, res->base | 1 << 1); |
| 112 | |
| 113 | } |
| 114 | |
| 115 | /** |
| 116 | * @brief Enable resources for children devices |
| 117 | * |
| 118 | * @param dev the device whos children's resources are to be enabled |
| 119 | * |
| 120 | */ |
| 121 | static void hudson_lpc_enable_childrens_resources(device_t dev) |
| 122 | { |
| 123 | printk(BIOS_DEBUG, "hudson_lpc_enable_childrens_resources\n"); |
| 124 | |
| 125 | } |
| 126 | |
| 127 | static void hudson_lpc_enable_resources(device_t dev) |
| 128 | { |
| 129 | pci_dev_enable_resources(dev); |
| 130 | hudson_lpc_enable_childrens_resources(dev); |
| 131 | } |
| 132 | |
| 133 | static struct pci_operations lops_pci = { |
| 134 | .set_subsystem = pci_dev_set_subsystem, |
| 135 | }; |
| 136 | |
| 137 | static struct device_operations lpc_ops = { |
| 138 | .read_resources = hudson_lpc_read_resources, |
| 139 | .set_resources = hudson_lpc_set_resources, |
| 140 | .enable_resources = hudson_lpc_enable_resources, |
| 141 | .init = lpc_init, |
| 142 | .scan_bus = scan_static_bus, |
| 143 | .ops_pci = &lops_pci, |
| 144 | }; |
| 145 | static const struct pci_driver lpc_driver __pci_driver = { |
| 146 | .ops = &lpc_ops, |
| 147 | .vendor = PCI_VENDOR_ID_AMD, |
| 148 | .device = PCI_DEVICE_ID_ATI_SB900_LPC, |
| 149 | }; |