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review.coreboot.org / coreboot / 3a75e5e8642d05d644ee3bccb92d8657ac2dadf0 / . / src / mainboard / google / falco / i915io.c
blob: e1479f24b728b86abe654c9d6d60c46bc9a90d3e [file] [log] [blame]
Ronald G. Minnich2120e0e22013-10-09 15:53:43 -0700[diff] [blame]1/*
2* This file is part of the coreboot project.
3*
4* Copyright 2013 Google Inc.
5*
6* This program is free software; you can redistribute it and/or modify
7* it under the terms of the GNU General Public License as published by
8* the Free Software Foundation; version 2 of the License.
9*
10* This program is distributed in the hope that it will be useful,
11* but WITHOUT ANY WARRANTY; without even the implied warranty of
12* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13* GNU General Public License for more details.
14*
15* You should have received a copy of the GNU General Public License
16* along with this program; if not, write to the Free Software
17* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18*/
19
20/* This code was originally generated using an i915tool program. It has been
21 * improved by hand.
22 */
23
24#include <stdint.h>
25#include <console/console.h>
26#include <delay.h>
27#include <drivers/intel/gma/i915.h>
28#include <arch/io.h>
29#include "mainboard.h"
30
Ronald G. Minnich2120e0e22013-10-09 15:53:43 -0700[diff] [blame]31/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
32void runio(struct intel_dp *dp);
33
34void runio(struct intel_dp *dp)
35{
36 u8 read_val;
37
38 intel_dp_wait_panel_power_control(0xabcd0008);
39
40 /* vbios spins at this point. Some haswell weirdness? */
41 intel_dp_wait_panel_power_control(0xabcd0008);
42
43 /* This should be a function like intel_panel_enable_backlight
44 However, we are not sure how the value 0x3a9 comes up.
45 It has to do something with PWM frequency */
46 gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
47 gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
48 gtt_write(BLC_PWM_PCH_CTL1,BLM_PCH_PWM_ENABLE);
49
50 gtt_write(DEIIR,0x00008000);
51 intel_dp_wait_reg(DEIIR, 0x00000000);
52
53 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
54
55 intel_dp_sink_dpms(dp, 0);
56
57 intel_dp_get_max_downspread(dp, &read_val);
58
59 intel_dp_set_m_n_regs(dp);
60
61 intel_dp_set_resolution(dp);
62
63 gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
64 gtt_write(PIPECONF(dp->transcoder),0x00000000);
65 gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
66
67 mainboard_set_port_clk_dp(dp);
68 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
Ronald G. Minnich3a75e5e2013-10-28 15:01:54 -0700[diff] [blame^]69 gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888);
Ronald G. Minnich2120e0e22013-10-09 15:53:43 -0700[diff] [blame]70 gtt_write(DEIIR,0x00000080);
71
72 gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
73 gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
74
75 intel_dp_wait_panel_power_control(0xabcd000a);
76
77 /* what is this doing? Not sure yet. */
78 intel_dp_i2c_write(dp, 0x0);
79 intel_dp_i2c_read(dp, &read_val);
80 intel_dp_i2c_write(dp, 0x04);
81 intel_dp_i2c_read(dp, &read_val);
82 intel_dp_i2c_write(dp, 0x7e);
83 intel_dp_i2c_read(dp, &read_val);
84
85 /* this needs to be a call to a function */
86 gtt_write(DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091);
87 gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
88 gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091);
89
90 /* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */
91 gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a);
92 gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a);
93
94 intel_dp_set_bw(dp);
95 intel_dp_set_lane_count(dp);
96
97 mainboard_train_link(dp);
98
99 /* need a function: intel_ddi_set_tp or similar */
100 gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_IDLE);
101 gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_NORMAL);
102
103 gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
104 gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
105 gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
106
107 /* some of this is not needed. */
108 gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
109
110 gtt_write(SDEIIR,0x00000000);
111 gtt_write(DEIIR,0x00000000);
112 gtt_write(DEIIR,0x00008000);
113 intel_dp_wait_reg(DEIIR, 0x00000000);
114
115 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
116 gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
117
118 gtt_write(DEIIR,0x00000080);
119 intel_dp_wait_reg(DEIIR, 0x00000000);
120
121 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
Ronald G. Minnich3a75e5e2013-10-28 15:01:54 -0700[diff] [blame^]122 gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
Ronald G. Minnich2120e0e22013-10-09 15:53:43 -0700[diff] [blame]123
124 gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON);
125
126 gtt_write(SDEIIR,0x00000000);
127 gtt_write(SDEIIR,0x00000000);
128 gtt_write(DEIIR,0x00000000);
129}