Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* |
| 4 | * This file is created based on Intel Alder Lake Processor PCH Datasheet |
| 5 | * Document number: 621483 |
| 6 | * Chapter number: 4 |
| 7 | */ |
| 8 | |
| 9 | #include <acpi/acpigen.h> |
| 10 | #include <console/console.h> |
| 11 | #include <device/mmio.h> |
| 12 | #include <device/device.h> |
| 13 | #include <drivers/intel/pmc_mux/chip.h> |
Tim Wawrzynczak | 5faee2e | 2021-07-01 08:24:18 -0600 | [diff] [blame] | 14 | #include <intelblocks/acpi.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 15 | #include <intelblocks/pmc.h> |
Tim Wawrzynczak | cbd2abf | 2021-06-03 14:11:21 -0600 | [diff] [blame] | 16 | #include <intelblocks/pmc_ipc.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 17 | #include <intelblocks/pmclib.h> |
| 18 | #include <intelblocks/rtc.h> |
Tim Wawrzynczak | 5faee2e | 2021-07-01 08:24:18 -0600 | [diff] [blame] | 19 | #include <soc/cpu.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 20 | #include <soc/pci_devs.h> |
| 21 | #include <soc/pm.h> |
| 22 | #include <soc/soc_chip.h> |
| 23 | #include <stdint.h> |
Kane Chen | 3aee3ad | 2021-05-04 09:53:38 +0800 | [diff] [blame] | 24 | #include <bootstate.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 25 | |
| 26 | #define PMC_HID "INTC1026" |
| 27 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 28 | static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) |
| 29 | { |
| 30 | uint32_t reg; |
| 31 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 32 | |
| 33 | printk(BIOS_DEBUG, "%sabling Deep S%c\n", |
| 34 | enable ? "En" : "Dis", sx + '0'); |
| 35 | reg = read32(pmcbase + offset); |
| 36 | if (enable) |
| 37 | reg |= mask; |
| 38 | else |
| 39 | reg &= ~mask; |
| 40 | write32(pmcbase + offset, reg); |
| 41 | } |
| 42 | |
| 43 | static void config_deep_s5(int on_ac, int on_dc) |
| 44 | { |
| 45 | /* Treat S4 the same as S5. */ |
| 46 | config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); |
| 47 | config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); |
| 48 | config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); |
| 49 | config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); |
| 50 | } |
| 51 | |
| 52 | static void config_deep_s3(int on_ac, int on_dc) |
| 53 | { |
| 54 | config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); |
| 55 | config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); |
| 56 | } |
| 57 | |
| 58 | static void config_deep_sx(uint32_t deepsx_config) |
| 59 | { |
| 60 | uint32_t reg; |
| 61 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 62 | |
| 63 | reg = read32(pmcbase + DSX_CFG); |
| 64 | reg &= ~DSX_CFG_MASK; |
| 65 | reg |= deepsx_config; |
| 66 | write32(pmcbase + DSX_CFG, reg); |
| 67 | } |
| 68 | |
| 69 | static void pmc_init(struct device *dev) |
| 70 | { |
| 71 | const config_t *config = config_of_soc(); |
| 72 | |
| 73 | rtc_init(); |
| 74 | |
| 75 | pmc_set_power_failure_state(true); |
| 76 | pmc_gpe_init(); |
| 77 | |
| 78 | config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); |
| 79 | config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); |
| 80 | config_deep_sx(config->deep_sx_config); |
| 81 | } |
| 82 | |
| 83 | static void soc_pmc_read_resources(struct device *dev) |
| 84 | { |
| 85 | struct resource *res; |
| 86 | |
| 87 | /* Add the fixed MMIO resource */ |
| 88 | mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); |
| 89 | |
| 90 | /* Add the fixed I/O resource */ |
| 91 | res = new_resource(dev, 1); |
| 92 | res->base = (resource_t)ACPI_BASE_ADDRESS; |
| 93 | res->size = (resource_t)ACPI_BASE_SIZE; |
| 94 | res->limit = res->base + res->size - 1; |
| 95 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 96 | } |
| 97 | |
| 98 | static void soc_pmc_fill_ssdt(const struct device *dev) |
| 99 | { |
| 100 | const char *scope = acpi_device_scope(dev); |
| 101 | const char *name = acpi_device_name(dev); |
| 102 | if (!scope || !name) |
| 103 | return; |
| 104 | |
| 105 | acpigen_write_scope(scope); |
| 106 | acpigen_write_device(name); |
| 107 | |
| 108 | acpigen_write_name_string("_HID", PMC_HID); |
| 109 | acpigen_write_name_string("_DDN", "Intel(R) Alder Lake IPC Controller"); |
| 110 | |
| 111 | /* |
| 112 | * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). |
| 113 | * The PMC gets 0xFE000000 - 0xFE00FFFF. |
| 114 | */ |
| 115 | acpigen_write_name("_CRS"); |
| 116 | acpigen_write_resourcetemplate_header(); |
| 117 | acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE); |
| 118 | acpigen_write_resourcetemplate_footer(); |
| 119 | |
Tim Wawrzynczak | cbd2abf | 2021-06-03 14:11:21 -0600 | [diff] [blame] | 120 | /* Define IPC Write Method */ |
| 121 | if (CONFIG(PMC_IPC_ACPI_INTERFACE)) |
| 122 | pmc_ipc_acpi_fill_ssdt(); |
| 123 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 124 | acpigen_pop_len(); /* PMC Device */ |
| 125 | acpigen_pop_len(); /* Scope */ |
| 126 | |
Tim Wawrzynczak | 5faee2e | 2021-07-01 08:24:18 -0600 | [diff] [blame] | 127 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) { |
| 128 | const struct soc_pmc_lpm adl_pmc_lpm = { |
| 129 | .num_substates = 8, |
| 130 | .num_req_regs = 6, |
| 131 | .lpm_ipc_offset = 0x1000, |
| 132 | .req_reg_stride = 0x30, |
| 133 | .lpm_enable_mask = get_supported_lpm_mask(), |
| 134 | }; |
| 135 | |
| 136 | generate_acpi_power_engine_with_lpm(&adl_pmc_lpm); |
| 137 | } |
| 138 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 139 | printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, |
| 140 | dev_path(dev)); |
| 141 | } |
| 142 | |
| 143 | static void soc_acpi_mode_init(struct device *dev) |
| 144 | { |
| 145 | /* |
| 146 | * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order |
| 147 | * to ensure the ordering does not break the assumptions that other |
| 148 | * drivers make about ACPI mode (e.g. Chrome EC). Since it disables |
| 149 | * ACPI mode, other drivers may take different actions based on this |
| 150 | * (e.g. Chrome EC will flush any pending hostevent bits). Because |
| 151 | * TGL has its PMC device available for device_operations, it can be |
| 152 | * done from the "ops->init" callback. |
| 153 | */ |
| 154 | pmc_set_acpi_mode(); |
| 155 | } |
| 156 | |
Kane Chen | 3aee3ad | 2021-05-04 09:53:38 +0800 | [diff] [blame] | 157 | static void pm1_enable_pwrbtn_smi(void *unused) |
| 158 | { |
| 159 | /* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */ |
| 160 | pmc_update_pm1_enable(PWRBTN_EN); |
| 161 | } |
| 162 | |
| 163 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); |
| 164 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 165 | struct device_operations pmc_ops = { |
| 166 | .read_resources = soc_pmc_read_resources, |
| 167 | .set_resources = noop_set_resources, |
| 168 | .init = soc_acpi_mode_init, |
| 169 | .enable = pmc_init, |
| 170 | #if CONFIG(HAVE_ACPI_TABLES) |
| 171 | .acpi_fill_ssdt = soc_pmc_fill_ssdt, |
| 172 | #endif |
| 173 | .scan_bus = scan_static_bus, |
| 174 | }; |