Dennis Wassenberg | bd10516 | 2015-09-10 12:20:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 secunet Security Networks AG |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Dennis Wassenberg | bd10516 | 2015-09-10 12:20:58 +0200 | [diff] [blame] | 19 | #include <device/pnp.h> |
| 20 | #include <northbridge/intel/sandybridge/raminit.h> |
| 21 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 22 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 23 | #include <southbridge/intel/bd82x6x/pch.h> |
| 24 | #include <superio/ite/it8783ef/it8783ef.h> |
| 25 | #include <superio/ite/common/ite.h> |
| 26 | |
| 27 | void pch_enable_lpc(void) |
| 28 | { |
| 29 | /* COMA on 0x3f8, COMB on 0x2f8 */ |
| 30 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
| 31 | /* Enable KBC on 0x60/0x64 (KBC), |
| 32 | EC on 0x62/0x66 (MC), |
| 33 | SIO on 0x2e/0x2f (CNF1) */ |
| 34 | pci_write_config16(PCH_LPC_DEV, LPC_EN, |
| 35 | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | |
| 36 | COMB_LPC_EN | COMA_LPC_EN); |
| 37 | } |
| 38 | |
| 39 | void mainboard_config_superio(void) |
| 40 | { |
| 41 | const pnp_devfn_t dev = PNP_DEV(0x2e, IT8783EF_GPIO); |
| 42 | |
| 43 | pnp_enter_conf_state(dev); |
| 44 | pnp_set_logical_device(dev); |
| 45 | |
| 46 | pnp_write_config(dev, 0x23, ITE_UART_CLK_PREDIVIDE_24); |
| 47 | |
| 48 | /* Switch multi function for UART4 */ |
| 49 | pnp_write_config(dev, 0x2a, 0x04); |
| 50 | /* Switch multi function for UART3 */ |
| 51 | pnp_write_config(dev, 0x2c, 0x13); |
| 52 | |
| 53 | /* No GPIOs used: Clear any output / pull-up that's set by default */ |
| 54 | pnp_write_config(dev, 0xb8, 0x00); |
| 55 | pnp_write_config(dev, 0xc0, 0x00); |
| 56 | pnp_write_config(dev, 0xc3, 0x00); |
| 57 | pnp_write_config(dev, 0xc8, 0x00); |
| 58 | pnp_write_config(dev, 0xcb, 0x00); |
| 59 | pnp_write_config(dev, 0xef, 0x00); |
| 60 | |
| 61 | pnp_exit_conf_state(dev); |
| 62 | } |
| 63 | |
| 64 | void mainboard_fill_pei_data(struct pei_data *const pei_data) |
| 65 | { |
| 66 | const struct pei_data pei_data_template = { |
| 67 | .pei_version = PEI_VERSION, |
| 68 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 69 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
| 70 | .epbar = DEFAULT_EPBAR, |
| 71 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 72 | .smbusbar = SMBUS_IO_BASE, |
| 73 | .wdbbar = 0x4000000, |
| 74 | .wdbsize = 0x1000, |
| 75 | .hpet_address = CONFIG_HPET_ADDRESS, |
| 76 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
| 77 | .pmbase = DEFAULT_PMBASE, |
| 78 | .gpiobase = DEFAULT_GPIOBASE, |
| 79 | .thermalbase = 0xfed08000, |
| 80 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 81 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 82 | .spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 }, |
| 83 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 84 | .ec_present = 1, |
| 85 | .gbe_enable = 1, |
| 86 | .ddr3lv_support = 0, |
| 87 | // 0 = leave channel enabled |
| 88 | // 1 = disable dimm 0 on channel |
| 89 | // 2 = disable dimm 1 on channel |
| 90 | // 3 = disable dimm 0+1 on channel |
| 91 | .dimm_channel0_disabled = 0, |
| 92 | .dimm_channel1_disabled = 0, |
| 93 | .max_ddr3_freq = 1600, |
| 94 | .usb_port_config = { |
| 95 | /* Enabled / OC PIN / Length */ |
| 96 | { 1, 0, 0x0080 }, /* P00: 1st (left) USB3 (OC #0) */ |
| 97 | { 1, 0, 0x0080 }, /* P01: 2nd (left) USB3 (OC #0) */ |
| 98 | { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ |
| 99 | { 1, 1, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #1) */ |
| 100 | { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ |
| 101 | { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ |
| 102 | { 1, 8, 0x0040 }, /* P06: USB Hub x4 USB2 (no OC) */ |
| 103 | { 1, 8, 0x0040 }, /* P07: MiniPCIe 4 USB2 (no OC) */ |
| 104 | { 1, 8, 0x0080 }, /* P08: SD card reader USB2 (no OC) */ |
| 105 | { 1, 4, 0x0080 }, /* P09: 3rd (right) USB2 (OC #4) */ |
| 106 | { 1, 5, 0x0040 }, /* P10: 4th (right) USB2 (OC #5) */ |
| 107 | { 1, 8, 0x0040 }, /* P11: 3rd Multibay USB2 (no OC) */ |
| 108 | { 1, 8, 0x0080 }, /* P12: misc internal USB2 (no OC) */ |
| 109 | { 1, 6, 0x0080 }, /* P13: misc internal USB2 (OC #6) */ |
| 110 | }, |
| 111 | .usb3 = { |
| 112 | .mode = 3, /* Smart Auto? */ |
| 113 | .hs_port_switch_mask = 0xf, /* All four ports. */ |
| 114 | .preboot_support = 1, /* preOS driver? */ |
| 115 | .xhci_streams = 1, /* Enable. */ |
| 116 | }, |
| 117 | .pcie_init = 1, |
| 118 | }; |
| 119 | *pei_data = pei_data_template; |
| 120 | } |
| 121 | |
| 122 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 123 | /* Enabled / Power / OC PIN */ |
| 124 | { 1, 1, 0 }, /* P00: 1st (left) USB3 (OC #0) */ |
| 125 | { 1, 1, 0 }, /* P01: 2nd (left) USB3 (OC #0) */ |
| 126 | { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */ |
| 127 | { 1, 1, 1 }, /* P03: 2nd Multibay USB3 (OC #1) */ |
| 128 | { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */ |
| 129 | { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */ |
| 130 | { 1, 0, 8 }, /* P06: USB Hub x4 USB2 (no OC) */ |
| 131 | { 1, 0, 8 }, /* P07: MiniPCIe 4 USB2 (no OC) */ |
| 132 | { 1, 1, 8 }, /* P08: SD card reader USB2 (no OC) */ |
| 133 | { 1, 1, 4 }, /* P09: 3rd (right) USB2 (OC #4) */ |
| 134 | { 1, 0, 5 }, /* P10: 4th (right) USB2 (OC #5) */ |
| 135 | { 1, 0, 8 }, /* P11: 3rd Multibay USB2 (no OC) */ |
| 136 | { 1, 1, 8 }, /* P12: misc internal USB2 (no OC) */ |
| 137 | { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */ |
| 138 | }; |
| 139 | |
| 140 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 141 | { |
| 142 | read_spd(&spd[0], 0x50, id_only); |
| 143 | read_spd(&spd[1], 0x51, id_only); |
| 144 | read_spd(&spd[2], 0x52, id_only); |
| 145 | read_spd(&spd[3], 0x53, id_only); |
| 146 | } |