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Lee Leahyc1e4f892016-01-07 11:24:24 -08001<!DOCTYPE html>
2<html>
3 <head>
4 <title>SoC</title>
5 </head>
6 <body>
7
8<h1>x86 System on a Chip (SoC) Development</h1>
9<p>
10 SoC development is best done in parallel with development for a specific
11 board. The combined steps are listed
12 <a target="_blank" href="../x86Development.html">here</a>.
13 The development steps for the SoC are listed below:
14</p>
15<ol>
16 <li><a target="_blank" href="../fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
17 <li>SoC <a href="#RequiredFiles">Required Files</a></li>
18 <li><a href="#Descriptor">Start Booting</a></li>
19 <li><a href="#EarlyDebug">Early Debug</a></li>
Lee Leahy380e1672016-01-31 10:49:35 -080020 <li><a href="#Bootblock">Bootblock</a></li>
Lee Leahyc1e4f892016-01-07 11:24:24 -080021</ol>
22
23
24<hr>
25<h1><a name="RequiredFiles">Required Files</a></h1>
26<p>
27 Create the directory as src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;.
28</p>
29
30<p>
31 The following files are required to build a new SoC:
32</p>
33<ul>
34 <li>Include files
35 <ul>
36 <li>include/soc/pei_data.h</li>
37 <li>include/soc/pm.h</li>
38 </ul>
39 </li>
40 <li>Kconfig - Defines the Kconfig value for the SoC and selects the tool
41 chains for the various stages:
42 <ul>
43 <li>select ARCH_BOOTBLOCK_&lt;Tool Chain&gt;</li>
44 <li>select ARCH_RAMSTAGE_&lt;Tool Chain&gt;</li>
45 <li>select ARCH_ROMSTAGE_&lt;Tool Chain&gt;</li>
46 <li>select ARCH_VERSTAGE_&lt;Tool Chain&gt;</li>
47 </ul>
48 </li>
49 <li>Makefile.inc - Specify the include paths</li>
50 <li>memmap.c - Top of usable RAM</li>
51</ul>
52
53
54<hr>
55<h1><a name="Descriptor">Start Booting</a></h1>
56<p>
57 Some SoC parts require additional firmware components in the flash.
58 This section describes how to add those pieces.
59</p>
60
61<h2>Intel Firmware Descriptor</h2>
62<p>
63 The Intel Firmware Descriptor (IFD) is located at the base of the flash part.
64 The following command overwrites the base of the flash image with the Intel
65 Firmware Descriptor:
66</p>
67<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre>
68
69
70<h2><a name="MEB">Management Engine Binary</a></h2>
71<p>
72 Some SoC parts contain and require that the Management Engine (ME) be running
73 before it is possible to bring the x86 processor out of reset. A binary file
74 containing the management engine code must be added to the firmware using the
75 ifdtool. The following commands add this binary blob:
76</p>
77<pre><code>util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom
78mv build/coreboot.rom.new build/coreboot.rom
79</code></pre>
80
81
82<h2><a name="EarlyDebug">Early Debug</a></h2>
83<p>
84 Early debugging between the reset vector and the time the serial port is enabled
85 is most easily done by writing values to port 0x80.
86</p>
87
88
89<h2>Success</h2>
90<p>
91 When the reset vector is successfully invoked, port 0x80 will output the following value:
92</p>
93<ul>
94 <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
95 - Bootblock successfully executed the
96 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
97 and entered the 16-bit code at
98 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
99 </li>
100</ul>
101
102
103<hr>
Lee Leahy380e1672016-01-31 10:49:35 -0800104<h1><a name="Bootblock">Bootblock</a></h1>
105<p>
106 Implement the bootblock using the following steps:
107</p>
108<ol>
109 <li>Create the directory as src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/bootblock</li>
110 <li>Add the timestamp.inc file which initializes the floating point registers and saves
111 the initial timestamp.
112 </li>
113 <li>Add the bootblock.c file which:
114 <ol type="A">
115 <li>Enables memory-mapped PCI config access</li>
116 <li>Updates the microcode by calling intel_update_microcode_from_cbfs</li>
117 <li>Enable ROM caching</li>
118 </ol>
119 </li>
120 <li>Edit the src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/Kconfig file
121 <ol type="A">
122 <li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li>
123 <li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li>
124 </ol>
125 </li>
126 <li>Edit the src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/Makefile.inc file
127 <ol type="A">
128 <li>Add the bootblock subdirectory</li>
129 </ol>
130 </li>
131 <li>Edit the src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/memmap.c file
132 <ol type="A">
133 <li>Add the fsp/memmap.h include file</li>
134 <li>Add the mmap_region_granularity routine</li>
135 </ol>
136 </li>
137 <li>Add the necessary .h files to define the necessary values and structures</li>
138 <li>When successful port 0x80 will output the following values:
139 <ol type="A">
140 <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
141 - Bootblock successfully executed the
142 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
143 and entered the 16-bit code at
144 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
145 </li>
146 <li>0x10: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l53">POST_ENTER_PROTECTED_MODE</a>
147 - Bootblock executing in
148 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc;hb=HEAD#l55">32-bit mode</a>
149 </li>
150 <li>0x10 - Verstage/romstage reached 32-bit mode</li>
151 </ol>
152 </li>
153</ol>
154
155<p>
156 <b>Build Note:</b> The following files are included into the default bootblock image:
157</p>
158<ul>
159 <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S;hb=HEAD">src/arch/x86/bootblock_romcc.S</a>
160 added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a>
161 and includes the following files:
162 <ul>
163 <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prologue.inc">src/arch/x86/prologue.inc</a></li>
164 <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc">src/cpu/x86/16bit/reset16.inc</a></li>
165 <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc">src/cpu/x86/16bit/entry16.inc</a></li>
166 <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc">src/cpu/x86/32bit/entry32.inc</a></li>
167 <li>The code in
168 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S">src/arch/x86/bootblock_romcc.S</a>
169 includes src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/bootblock/timestamp.inc using the
170 CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above
171 </li>
172 <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_enable.inc">src/cpu/x86/sse_enable.inc</a></li>
173 <li>The code in
174 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l156">src/arch/x86/Makefile.inc</a>
175 invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc:
176 <ul>
177 <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/bootblock_romcc.h">src/arch/x86/include/arch/bootblock_romcc.h</a></li>
178 <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/boot_cpu.c">src/cpu/x86/lapic/boot_cpu.c</a></li>
179 <li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in
180 src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/bootblock/bootblock.c
181 </li>
182 </ul>
183 </li>
184 </ul>
185 </li>
186 <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a>
187 added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a>
188 </li>
189 <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/fit.S">src/cpu/intel/fit/fit.S</a>
190 added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a>
191 </li>
192 <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkcbfs.S">src/arch/x86/walkcbfs.S</a>
193 added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a>
194 </li>
195</ul>
196
197
198<hr>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800199<p>Modified: 31 January 2016</p>
200 </body>
201</html>