Edward O'Callaghan | 956c298 | 2014-03-16 17:09:58 +1100 | [diff] [blame] | 1 | chip northbridge/intel/sandybridge |
| 2 | |
| 3 | # Enable DisplayPort Hotplug with 6ms pulse |
| 4 | register "gpu_dp_d_hotplug" = "0x06" |
| 5 | |
| 6 | # Enable Panel as LVDS and configure power delays |
| 7 | register "gpu_panel_port_select" = "0" # LVDS |
| 8 | register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms |
| 9 | register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms |
| 10 | register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms |
Edward O'Callaghan | 5fcae80 | 2014-07-29 14:42:26 +1000 | [diff] [blame] | 11 | register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms |
| 12 | register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 13 | register "gfx.use_spread_spectrum_clock" = "1" |
| 14 | register "gfx.lvds_dual_channel" = "1" |
| 15 | register "gfx.link_frequency_270_mhz" = "1" |
| 16 | register "gfx.lvds_num_lanes" = "1" |
Edward O'Callaghan | 5fcae80 | 2014-07-29 14:42:26 +1000 | [diff] [blame] | 17 | register "gpu_cpu_backlight" = "0x1155" |
| 18 | register "gpu_pch_backlight" = "0x11551155" |
Edward O'Callaghan | 956c298 | 2014-03-16 17:09:58 +1100 | [diff] [blame] | 19 | |
| 20 | device cpu_cluster 0 on |
| 21 | chip cpu/intel/socket_rPGA989 |
| 22 | device lapic 0 on end |
| 23 | end |
| 24 | chip cpu/intel/model_206ax |
| 25 | # Magic APIC ID to locate this chip |
| 26 | device lapic 0xACAC off end |
| 27 | |
| 28 | # Coordinate with HW_ALL |
| 29 | register "pstate_coord_type" = "0xfe" |
| 30 | |
| 31 | register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) |
| 32 | register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) |
| 33 | register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) |
| 34 | |
| 35 | register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) |
| 36 | register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) |
| 37 | register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) |
| 38 | end |
| 39 | end |
| 40 | |
| 41 | device domain 0 on |
| 42 | device pci 00.0 on end # host bridge |
Edward O'Callaghan | a812643 | 2014-09-13 06:53:20 +1000 | [diff] [blame] | 43 | device pci 01.0 on end # PCIe Bridge for discrete graphics |
Edward O'Callaghan | 956c298 | 2014-03-16 17:09:58 +1100 | [diff] [blame] | 44 | device pci 02.0 on end # vga controller |
| 45 | |
| 46 | chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH |
| 47 | register "pirqa_routing" = "0x8b" |
| 48 | register "pirqb_routing" = "0x8a" |
| 49 | register "pirqc_routing" = "0x8b" |
| 50 | register "pirqd_routing" = "0x8b" |
| 51 | register "pirqe_routing" = "0x80" |
| 52 | register "pirqf_routing" = "0x80" |
| 53 | register "pirqg_routing" = "0x80" |
| 54 | register "pirqh_routing" = "0x80" |
| 55 | |
| 56 | # GPI routing |
| 57 | # 0 No effect (default) |
| 58 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 59 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
| 60 | register "alt_gp_smi_en" = "0x0000" |
| 61 | register "gpi1_routing" = "2" |
| 62 | register "gpi8_routing" = "2" |
| 63 | |
Edward O'Callaghan | cf6f9b9 | 2014-09-13 06:06:05 +1000 | [diff] [blame] | 64 | # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) |
| 65 | register "sata_port_map" = "0x3f" |
Edward O'Callaghan | 956c298 | 2014-03-16 17:09:58 +1100 | [diff] [blame] | 66 | # Set max SATA speed to 6.0 Gb/s |
| 67 | register "sata_interface_speed_support" = "0x3" |
| 68 | |
| 69 | register "gen1_dec" = "0x7c1601" |
| 70 | register "gen2_dec" = "0x0c15e1" |
| 71 | register "gen4_dec" = "0x0c06a1" |
| 72 | |
| 73 | # Enable zero-based linear PCIe root port functions |
| 74 | register "pcie_port_coalesce" = "1" |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 75 | register "c2_latency" = "101" # c2 not supported |
| 76 | register "p_cnt_throttling_supported" = "1" |
Edward O'Callaghan | 956c298 | 2014-03-16 17:09:58 +1100 | [diff] [blame] | 77 | |
| 78 | device pci 14.0 on end # USB 3.0 Controller |
| 79 | device pci 16.0 on end # Management Engine Interface 1 |
| 80 | device pci 16.1 off end # Management Engine Interface 2 |
| 81 | device pci 16.2 off end # Management Engine IDE-R |
| 82 | device pci 16.3 off end # Management Engine KT |
| 83 | device pci 19.0 on end # Intel Gigabit Ethernet |
| 84 | device pci 1a.0 on end # USB2 EHCI #2 |
| 85 | device pci 1b.0 on end # High Definition Audio |
| 86 | device pci 1c.0 on end # PCIe Port #1 |
| 87 | device pci 1c.1 on end # PCIe Port #2 |
| 88 | device pci 1c.2 on end # PCIe Port #3 (expresscard) |
| 89 | device pci 1c.3 off end # PCIe Port #4 |
| 90 | device pci 1c.4 off end # PCIe Port #5 |
| 91 | device pci 1c.5 off end # PCIe Port #6 |
| 92 | device pci 1c.6 off end # PCIe Port #7 |
| 93 | device pci 1c.7 off end # PCIe Port #8 |
| 94 | device pci 1d.0 on end # USB2 EHCI #1 |
| 95 | device pci 1e.0 off end # PCI bridge |
| 96 | device pci 1f.0 on #LPC bridge |
| 97 | chip ec/lenovo/pmh7 |
| 98 | device pnp ff.1 on # dummy |
| 99 | end |
| 100 | register "backlight_enable" = "0x01" |
| 101 | register "dock_event_enable" = "0x01" |
| 102 | end |
| 103 | |
| 104 | chip ec/lenovo/h8 |
| 105 | device pnp ff.2 on # dummy |
| 106 | io 0x60 = 0x62 |
| 107 | io 0x62 = 0x66 |
| 108 | io 0x64 = 0x1600 |
| 109 | io 0x66 = 0x1604 |
| 110 | end |
| 111 | |
Edward O'Callaghan | fe365ac | 2014-03-16 17:24:18 +1100 | [diff] [blame] | 112 | register "config0" = "0xa7" |
Edward O'Callaghan | 956c298 | 2014-03-16 17:09:58 +1100 | [diff] [blame] | 113 | register "config1" = "0x09" |
| 114 | register "config2" = "0xa0" |
Edward O'Callaghan | fe365ac | 2014-03-16 17:24:18 +1100 | [diff] [blame] | 115 | register "config3" = "0xc2" |
Edward O'Callaghan | 956c298 | 2014-03-16 17:09:58 +1100 | [diff] [blame] | 116 | |
| 117 | register "has_keyboard_backlight" = "1" |
| 118 | |
| 119 | register "beepmask0" = "0x00" |
| 120 | register "beepmask1" = "0x86" |
| 121 | register "has_power_management_beeps" = "0" |
| 122 | register "event2_enable" = "0xff" |
| 123 | register "event3_enable" = "0xff" |
| 124 | register "event4_enable" = "0xd0" |
| 125 | register "event5_enable" = "0xfc" |
| 126 | register "event6_enable" = "0x00" |
| 127 | register "event7_enable" = "0x01" |
| 128 | register "event8_enable" = "0x7b" |
| 129 | register "event9_enable" = "0xff" |
| 130 | register "eventa_enable" = "0x01" |
| 131 | register "eventb_enable" = "0x00" |
| 132 | register "eventc_enable" = "0xff" |
| 133 | register "eventd_enable" = "0xff" |
| 134 | register "evente_enable" = "0x0d" |
| 135 | end |
| 136 | end # LPC bridge |
| 137 | device pci 1f.2 on end # SATA Controller 1 |
| 138 | device pci 1f.3 on |
| 139 | # eeprom, 8 virtual devices, same chip |
| 140 | chip drivers/i2c/at24rf08c |
| 141 | device i2c 54 on end |
| 142 | device i2c 55 on end |
| 143 | device i2c 56 on end |
| 144 | device i2c 57 on end |
| 145 | device i2c 5c on end |
| 146 | device i2c 5d on end |
| 147 | device i2c 5e on end |
| 148 | device i2c 5f on end |
| 149 | end |
| 150 | end # SMBus |
| 151 | device pci 1f.5 off end # SATA Controller 2 |
| 152 | device pci 1f.6 on end # Thermal |
| 153 | end |
| 154 | end |
| 155 | end |