blob: 183edf3eda50aebb8844e2e14305f981131f52c6 [file] [log] [blame]
Duncan Laurieea98b402018-10-15 13:45:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2018 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/io.h>
Kyösti Mälkki36955932019-03-03 17:43:29 +020017#include <endian.h>
Duncan Laurieea98b402018-10-15 13:45:29 -070018#include <device/pnp_def.h>
Duncan Laurieea98b402018-10-15 13:45:29 -070019
20#include "bootblock.h"
21
22#define PNP_CFG_IDX 0x2e
23#define PNP_LDN_SERIAL 0x0d
24
25static void pnp_enter_conf_state(pnp_devfn_t dev)
26{
27 outb(0x55, PNP_CFG_IDX);
28 outb(0x55, PNP_CFG_IDX);
29}
30
31static void pnp_exit_conf_state(pnp_devfn_t dev)
32{
33 outb(0xaa, PNP_CFG_IDX);
34}
35
36static void wilco_ec_serial_init(void)
37{
38 pnp_devfn_t dev = PNP_DEV(PNP_CFG_IDX, PNP_LDN_SERIAL);
39
40 pnp_enter_conf_state(dev);
41 pnp_set_logical_device(dev);
42 pnp_set_enable(dev, 1);
43 pnp_set_iobase(dev, PNP_IDX_IO1, cpu_to_be16(CONFIG_TTYS0_BASE));
44 pnp_write_config(dev, PNP_IDX_IO0, 1);
45 pnp_exit_conf_state(dev);
46}
47
48void wilco_ec_early_init(void)
49{
50 if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))
51 wilco_ec_serial_init();
52}