blob: 4ece5402fbde3df2da7af05c9fc2a463a13cef7e [file] [log] [blame]
Kyösti Mälkkicb08e162013-10-15 17:19:41 +03001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20// Use simple device model for this file even in ramstage
21#define __SIMPLE_DEVICE__
22
23#include <arch/io.h>
24#include <cbmem.h>
25#include "i945.h"
26
27unsigned long get_top_of_ram(void)
28{
29 u32 tom;
30
31 if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) {
32 /* IGD enabled, get top of Memory from BSM register */
33 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
34 } else {
35 tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
36 }
37
38 /* if TSEG enabled subtract size */
39 switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) {
40 case 0x01:
41 /* 1MB TSEG */
42 tom -= 0x10000;
43 break;
44 case 0x03:
45 /* 2MB TSEG */
46 tom -= 0x20000;
47 break;
48 case 0x05:
49 /* 8MB TSEG */
50 tom -= 0x80000;
51 break;
52 default:
53 /* TSEG either disabled or invalid */
54 break;
55 }
56 return (unsigned long) tom;
57}