Aaron Durbin | ae31f7d | 2013-11-22 14:16:49 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pciexp.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <reg_script.h> |
| 26 | |
| 27 | #include <baytrail/pci_devs.h> |
| 28 | #include <baytrail/pcie.h> |
| 29 | #include <baytrail/ramstage.h> |
| 30 | |
| 31 | #include "chip.h" |
| 32 | |
| 33 | static int pll_en_off; |
| 34 | static uint32_t strpfusecfg; |
| 35 | |
| 36 | static inline int root_port_offset(device_t dev) |
| 37 | { |
| 38 | return PCI_FUNC(dev->path.pci.devfn); |
| 39 | } |
| 40 | |
| 41 | static inline int is_first_port(device_t dev) |
| 42 | { |
| 43 | return root_port_offset(dev) == PCIE_PORT1_FUNC; |
| 44 | } |
| 45 | |
| 46 | static const struct reg_script init_static_before_exit_latency[] = { |
| 47 | /* Disable optimized buffer flush fill and latency tolerant reporting */ |
| 48 | REG_PCI_RMW32(DCAP2, ~(OBFFS | LTRMS), 0), |
| 49 | REG_PCI_RMW32(DSTS2, ~(OBFFEN| LTRME), 0), |
| 50 | /* Set maximum payload size. */ |
| 51 | REG_PCI_RMW32(DCAP, ~MPS_MASK, 0), |
| 52 | /* Disable transmit datapath flush timer, clear transmit config change |
| 53 | * wait time, clear sideband interface idle counter. */ |
| 54 | REG_PCI_RMW32(PHYCTL2_IOSFBCTL, ~(TDFT | TXCFGCHWAIT | SIID), 0), |
| 55 | REG_SCRIPT_END, |
| 56 | }; |
| 57 | |
| 58 | static const struct reg_script init_static_after_exit_latency[] = { |
| 59 | /* Set common clock configuration. */ |
| 60 | REG_PCI_OR16(LCTL, CCC), |
| 61 | /* Set NFTS to 0x743a361b */ |
| 62 | REG_PCI_WRITE32(NFTS, 0x743a361b), |
| 63 | /* Set common clock latency to 0x3 */ |
| 64 | REG_PCI_RMW32(MPC, ~CCEL_MASK, (0x3 << CCEL_SHIFT)), |
| 65 | /* Set relay timer policy. */ |
| 66 | REG_PCI_RMW32(RTP, 0xff000000, 0x854c74), |
| 67 | /* Set IOSF packet fast transmit mode and link speed training policy. */ |
| 68 | REG_PCI_OR16(MPC2, IPF | LSTP), |
| 69 | /* Channel configuration - enable upstream posted split, set non-posted |
| 70 | * and posted request size */ |
| 71 | REG_PCI_RMW32(CHCFG, ~UPSD, UNRS | UPRS), |
| 72 | /* Completion status replay enable and set TLP grant count */ |
| 73 | REG_PCI_RMW32(CFG2, ~(LATGC_MASK), CSREN | (3 << LATGC_SHIFT)), |
| 74 | /* Assume no IOAPIC behind root port -- disable EOI forwarding. */ |
| 75 | REG_PCI_OR16(MPC2, EOIFD), |
| 76 | /* Expose AER */ |
| 77 | REG_PCI_RMW32(AERCH, ~0, (1 << 16) | (1 << 0)), |
| 78 | /* set completion timeout to 160ms to 170ms */ |
| 79 | REG_PCI_RMW16(DSTS2, ~CTD, 0x6), |
| 80 | /* Enable AER */ |
| 81 | REG_PCI_OR16(DCTL_DSTS, URE | FEE | NFE | CEE), |
| 82 | /* Read and write back capabaility registers. */ |
| 83 | REG_PCI_OR32(0x34, 0), |
| 84 | REG_PCI_OR32(0x80, 0), |
| 85 | /* Retrain the link. */ |
| 86 | REG_PCI_OR16(LCTL, RL), |
| 87 | REG_SCRIPT_END, |
| 88 | }; |
| 89 | |
| 90 | static void byt_pcie_init(device_t dev) |
| 91 | { |
| 92 | struct reg_script init_script[] = { |
Aaron Durbin | ae31f7d | 2013-11-22 14:16:49 -0600 | [diff] [blame] | 93 | REG_SCRIPT_NEXT(init_static_before_exit_latency), |
| 94 | /* Exit latency configuration based on |
| 95 | * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ |
| 96 | REG_PCI_RMW32(LCAP, ~L1EXIT_MASK, |
| 97 | 2 << (L1EXIT_MASK + pll_en_off)), |
| 98 | REG_SCRIPT_NEXT(init_static_after_exit_latency), |
| 99 | /* Disable hot plug, set power to 10W, set slot number. */ |
| 100 | REG_PCI_RMW32(SLCAP, ~(HPC | HPS), |
| 101 | (1 << SLS_SHIFT) | (100 << SLV_SHIFT) | |
| 102 | (root_port_offset(dev) << SLN_SHIFT)), |
| 103 | /* Dynamic clock gating. */ |
| 104 | REG_PCI_OR32(RPPGEN, RPDLCGEN | RPDBCGEN | RPSCGEN), |
| 105 | REG_PCI_OR32(PWRCTL, RPL1SQPOL | RPDTSQPOL), |
| 106 | REG_PCI_OR32(PCIEDBG, SPCE), |
| 107 | REG_SCRIPT_END, |
| 108 | }; |
| 109 | |
Aaron Durbin | 616f394 | 2013-12-10 17:12:44 -0800 | [diff] [blame] | 110 | reg_script_run_on_dev(dev, init_script); |
Aaron Durbin | ae31f7d | 2013-11-22 14:16:49 -0600 | [diff] [blame] | 111 | |
| 112 | if (is_first_port(dev)) { |
| 113 | struct soc_intel_baytrail_config *config = dev->chip_info; |
| 114 | uint32_t reg = pci_read_config32(dev, RPPGEN); |
| 115 | reg |= SRDLCGEN | SRDBCGEN; |
| 116 | |
| 117 | if (config && config->clkreq_enable) |
| 118 | reg |= LCLKREQEN | BBCLKREQEN; |
| 119 | |
| 120 | pci_write_config32(dev, RPPGEN, reg); |
| 121 | } |
| 122 | } |
| 123 | |
| 124 | static const struct reg_script no_dev_behind_port[] = { |
| 125 | REG_PCI_OR32(PCIEALC, (1 << 26)), |
| 126 | REG_PCI_POLL32(PCIESTS1, 0x1f000000, (1 << 24), 50000), |
| 127 | REG_PCI_OR32(PHYCTL4, SQDIS), |
| 128 | REG_SCRIPT_END, |
| 129 | }; |
| 130 | |
| 131 | static void check_port_enabled(device_t dev) |
| 132 | { |
| 133 | int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; |
| 134 | |
| 135 | switch (root_port_offset(dev)) { |
| 136 | case PCIE_PORT1_FUNC: |
| 137 | /* Port 1 cannot be disabled from strapping config. */ |
| 138 | break; |
| 139 | case PCIE_PORT2_FUNC: |
| 140 | /* Port 2 disabled in all configs but 4x1. */ |
| 141 | if (rp_config != 0x0) |
| 142 | dev->enabled = 0; |
| 143 | break; |
| 144 | case PCIE_PORT3_FUNC: |
| 145 | /* Port 3 disabled only in 1x4 config. */ |
| 146 | if (rp_config == 0x3) |
| 147 | dev->enabled = 0; |
| 148 | break; |
| 149 | case PCIE_PORT4_FUNC: |
| 150 | /* Port 4 disabled in 1x4 and 2x2 config. */ |
| 151 | if (rp_config >= 0x2) |
| 152 | dev->enabled = 0; |
| 153 | break; |
| 154 | } |
| 155 | } |
| 156 | |
| 157 | static void check_device_present(device_t dev) |
| 158 | { |
Aaron Durbin | ae31f7d | 2013-11-22 14:16:49 -0600 | [diff] [blame] | 159 | /* Set slot implemented. */ |
| 160 | pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); |
| 161 | |
| 162 | /* No device present. */ |
| 163 | if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { |
| 164 | printk(BIOS_DEBUG, "No PCIe device present.\n"); |
Aaron Durbin | 616f394 | 2013-12-10 17:12:44 -0800 | [diff] [blame] | 165 | reg_script_run_on_dev(dev, no_dev_behind_port); |
Aaron Durbin | ae31f7d | 2013-11-22 14:16:49 -0600 | [diff] [blame] | 166 | dev->enabled = 0; |
| 167 | } else if(!dev->enabled) { |
| 168 | /* Port is disabled, but device present. Disable link. */ |
| 169 | pci_write_config32(dev, LCTL, |
| 170 | pci_read_config32(dev, LCTL) | LD); |
| 171 | } |
| 172 | } |
| 173 | |
| 174 | static void byt_pcie_enable(device_t dev) |
| 175 | { |
| 176 | if (is_first_port(dev)) { |
| 177 | uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); |
| 178 | pll_en_off = !!(reg & PLL_OFF_EN); |
| 179 | |
| 180 | strpfusecfg = pci_read_config32(dev, STRPFUSECFG); |
| 181 | } |
| 182 | |
| 183 | /* Check if device is enabled in strapping. */ |
| 184 | check_port_enabled(dev); |
| 185 | /* Determine if device is behind port. */ |
| 186 | check_device_present(dev); |
| 187 | |
| 188 | southcluster_enable_dev(dev); |
| 189 | } |
| 190 | |
| 191 | static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) |
| 192 | { |
| 193 | uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); |
| 194 | |
| 195 | if (!didvid) |
| 196 | didvid = pci_read_config32(dev, PCI_VENDOR_ID); |
| 197 | pci_write_config32(dev, 0x94, didvid); |
| 198 | } |
| 199 | |
| 200 | static struct pci_operations pcie_root_ops = { |
| 201 | .set_subsystem = &pcie_root_set_subsystem, |
| 202 | }; |
| 203 | |
| 204 | static struct device_operations device_ops = { |
| 205 | .read_resources = pci_bus_read_resources, |
| 206 | .set_resources = pci_dev_set_resources, |
| 207 | .enable_resources = pci_bus_enable_resources, |
| 208 | .init = byt_pcie_init, |
| 209 | .scan_bus = pciexp_scan_bridge, |
| 210 | .enable = byt_pcie_enable, |
| 211 | .ops_pci = &pcie_root_ops, |
| 212 | }; |
| 213 | |
| 214 | static const unsigned short pci_device_ids[] = { |
| 215 | PCIE_PORT1_DEVID, PCIE_PORT2_DEVID, PCIE_PORT3_DEVID, PCIE_PORT4_DEVID, |
| 216 | 0 |
| 217 | }; |
| 218 | |
| 219 | static const struct pci_driver pcie_root_ports __pci_driver = { |
| 220 | .ops = &device_ops, |
| 221 | .vendor = PCI_VENDOR_ID_INTEL, |
| 222 | .devices = pci_device_ids, |
| 223 | }; |