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Jason Schildt043b4092005-08-10 15:16:44 +00001/*
Yinghai Lud4b278c2006-10-04 20:46:15 +00002 This should be done by Eric
3 2004.12 yhlu add multi ht chain dynamically support
4 2005.11 yhlu add let real sb to use small unitid
5*/
Eric Biederman5cd81732004-03-11 15:01:31 +00006#include <device/pci_def.h>
7#include <device/pci_ids.h>
8#include <device/hypertransport_def.h>
9
Myles Watsond61ada62008-10-02 19:20:22 +000010// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
Stefan Reinauer7ce8c542005-12-02 21:52:30 +000011#ifndef K8_ALLOCATE_MMIO_RANGE
Myles Watsond61ada62008-10-02 19:20:22 +000012 #define K8_ALLOCATE_MMIO_RANGE 0
Stefan Reinauer7ce8c542005-12-02 21:52:30 +000013#endif
14
Jason Schildt043b4092005-08-10 15:16:44 +000015static inline void print_linkn_in (const char *strval, uint8_t byteval)
Yinghai Lu1bc56542005-01-06 02:23:31 +000016{
Stefan Reinauer64ed2b72010-03-31 14:47:43 +000017 printk(BIOS_DEBUG, "%s%02x\n", strval, byteval);
Yinghai Lu1bc56542005-01-06 02:23:31 +000018}
19
Jason Schildt043b4092005-08-10 15:16:44 +000020static uint8_t ht_lookup_capability(device_t dev, uint16_t val)
Eric Biederman5cd81732004-03-11 15:01:31 +000021{
Jason Schildt043b4092005-08-10 15:16:44 +000022 uint8_t pos;
23 uint8_t hdr_type;
Eric Biederman5cd81732004-03-11 15:01:31 +000024
25 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
26 pos = 0;
27 hdr_type &= 0x7f;
28
29 if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
Jason Schildt043b4092005-08-10 15:16:44 +000030 (hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
Eric Biederman5cd81732004-03-11 15:01:31 +000031 pos = PCI_CAPABILITY_LIST;
32 }
33 if (pos > PCI_CAP_LIST_NEXT) {
34 pos = pci_read_config8(dev, pos);
35 }
Yinghai Lud4b278c2006-10-04 20:46:15 +000036 while(pos != 0) { /* loop through the linked list */
Jason Schildt043b4092005-08-10 15:16:44 +000037 uint8_t cap;
Eric Biederman5cd81732004-03-11 15:01:31 +000038 cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
39 if (cap == PCI_CAP_ID_HT) {
Jason Schildt043b4092005-08-10 15:16:44 +000040 uint16_t flags;
Eric Biederman5cd81732004-03-11 15:01:31 +000041
42 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
Jason Schildt043b4092005-08-10 15:16:44 +000043 if ((flags >> 13) == val) {
44 /* Entry is a slave or host , success... */
Eric Biederman5cd81732004-03-11 15:01:31 +000045 break;
46 }
47 }
48 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
49 }
50 return pos;
51}
52
Jason Schildt043b4092005-08-10 15:16:44 +000053static uint8_t ht_lookup_slave_capability(device_t dev)
Myles Watsond61ada62008-10-02 19:20:22 +000054{
Jason Schildt043b4092005-08-10 15:16:44 +000055 return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format
56}
57
Stefan Reinauereea66b72010-04-07 15:32:52 +000058#if 0
Jason Schildt043b4092005-08-10 15:16:44 +000059static uint8_t ht_lookup_host_capability(device_t dev)
60{
Myles Watsond61ada62008-10-02 19:20:22 +000061 return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
Jason Schildt043b4092005-08-10 15:16:44 +000062}
Stefan Reinauereea66b72010-04-07 15:32:52 +000063#endif
Jason Schildt043b4092005-08-10 15:16:44 +000064
Stefan Reinauer7ce8c542005-12-02 21:52:30 +000065static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid)
Eric Biederman5cd81732004-03-11 15:01:31 +000066{
67 device_t dev;
Jason Schildt043b4092005-08-10 15:16:44 +000068
Yinghai Lud4b278c2006-10-04 20:46:15 +000069 //actually, only for one HT device HT chain, and unitid is 0
Stefan Reinauer08670622009-06-30 15:17:49 +000070#if CONFIG_HT_CHAIN_UNITID_BASE == 0
Stefan Reinauer7ce8c542005-12-02 21:52:30 +000071 if(offset_unitid) {
72 return;
73 }
74#endif
75
Jason Schildt043b4092005-08-10 15:16:44 +000076 /* Check if is already collapsed */
Stefan Reinauer08670622009-06-30 15:17:49 +000077 if((!offset_unitid) || (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) {
Myles Watsonfa12b672009-04-30 22:45:41 +000078 uint32_t id;
Stefan Reinauer7ce8c542005-12-02 21:52:30 +000079 dev = PCI_DEV(bus, 0, 0);
Myles Watsond61ada62008-10-02 19:20:22 +000080 id = pci_read_config32(dev, PCI_VENDOR_ID);
81 if (!((id == 0xffffffff) || (id == 0x00000000) ||
82 (id == 0x0000ffff) || (id == 0xffff0000))) {
83 return;
84 }
85 }
Jason Schildt043b4092005-08-10 15:16:44 +000086
Eric Biederman5cd81732004-03-11 15:01:31 +000087 /* Spin through the devices and collapse any previous
88 * hypertransport enumeration.
89 */
Yinghai Lu2c956bb2004-12-17 21:08:16 +000090 for(dev = PCI_DEV(bus, 1, 0); dev <= PCI_DEV(bus, 0x1f, 0x7); dev += PCI_DEV(0, 1, 0)) {
Jason Schildt043b4092005-08-10 15:16:44 +000091 uint32_t id;
92 uint8_t pos;
93 uint16_t flags;
Myles Watsond61ada62008-10-02 19:20:22 +000094
Eric Biederman5cd81732004-03-11 15:01:31 +000095 id = pci_read_config32(dev, PCI_VENDOR_ID);
Jason Schildt043b4092005-08-10 15:16:44 +000096 if ((id == 0xffffffff) || (id == 0x00000000) ||
97 (id == 0x0000ffff) || (id == 0xffff0000)) {
Eric Biederman5cd81732004-03-11 15:01:31 +000098 continue;
99 }
Myles Watsond61ada62008-10-02 19:20:22 +0000100
Eric Biederman5cd81732004-03-11 15:01:31 +0000101 pos = ht_lookup_slave_capability(dev);
102 if (!pos) {
103 continue;
104 }
Yinghai Lu6a61d6a2004-10-20 05:07:16 +0000105
Eric Biederman5cd81732004-03-11 15:01:31 +0000106 /* Clear the unitid */
107 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
108 flags &= ~0x1f;
109 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
110 }
111}
112
Jason Schildt043b4092005-08-10 15:16:44 +0000113static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
Eric Biederman5cd81732004-03-11 15:01:31 +0000114{
115 /* Handle bugs in valid hypertransport frequency reporting */
Jason Schildt043b4092005-08-10 15:16:44 +0000116 uint16_t freq_cap;
117 uint32_t id;
Eric Biederman5cd81732004-03-11 15:01:31 +0000118
119 freq_cap = pci_read_config16(dev, pos);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000120 printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap);
Eric Biederman5cd81732004-03-11 15:01:31 +0000121 freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
122
123 id = pci_read_config32(dev, 0);
124
125 /* AMD 8131 Errata 48 */
126 if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8131_PCIX << 16))) {
127 freq_cap &= ~(1 << HT_FREQ_800Mhz);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000128 return freq_cap;
129 }
arch import user (historical)98d0d302005-07-06 17:13:46 +0000130
Eric Biederman5cd81732004-03-11 15:01:31 +0000131 /* AMD 8151 Errata 23 */
132 if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8151_SYSCTRL << 16))) {
133 freq_cap &= ~(1 << HT_FREQ_800Mhz);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000134 return freq_cap;
Myles Watsond61ada62008-10-02 19:20:22 +0000135 }
136
Eric Biederman5cd81732004-03-11 15:01:31 +0000137 /* AMD K8 Unsupported 1Ghz? */
138 if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
Stefan Reinauer08670622009-06-30 15:17:49 +0000139 #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
140 #if CONFIG_K8_REV_F_SUPPORT == 0
Myles Watsond61ada62008-10-02 19:20:22 +0000141 if (is_cpu_pre_e0()) { // only E0 later support 1GHz
Jason Schildtcf6df2a2005-10-25 21:41:45 +0000142 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000143 }
Yinghai Lud4b278c2006-10-04 20:46:15 +0000144 #endif
Myles Watsond61ada62008-10-02 19:20:22 +0000145 #else
146 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000147 #endif
Eric Biederman5cd81732004-03-11 15:01:31 +0000148 }
arch import user (historical)98d0d302005-07-06 17:13:46 +0000149
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000150 printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);
Rudolf Marek23b21522011-06-29 23:47:20 +0200151
152 #if CONFIG_SOUTHBRIDGE_VIA_K8M890 == 1
153 freq_cap &= 0x3f;
154 printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n");
155 #endif
Eric Biederman5cd81732004-03-11 15:01:31 +0000156 return freq_cap;
157}
Myles Watsond61ada62008-10-02 19:20:22 +0000158
Yinghai Lu00a018f2007-04-06 21:06:44 +0000159static uint8_t ht_read_width_cap(device_t dev, uint8_t pos)
160{
161 uint8_t width_cap = pci_read_config8(dev, pos);
162
163 uint32_t id;
164
165 id = pci_read_config32(dev, 0);
166
167 /* netlogic micro cap doesn't support 16 bit yet */
168 if (id == (0x184e | (0x0001 << 16))) {
169 if((width_cap & 0x77) == 0x11) {
170 width_cap &= 0x88;
171 }
172 }
Myles Watsond61ada62008-10-02 19:20:22 +0000173
Yinghai Lu00a018f2007-04-06 21:06:44 +0000174 return width_cap;
Myles Watsond61ada62008-10-02 19:20:22 +0000175
Yinghai Lu00a018f2007-04-06 21:06:44 +0000176}
Myles Watsond61ada62008-10-02 19:20:22 +0000177
Jason Schildt6e44b422005-08-09 21:53:07 +0000178#define LINK_OFFS(CTRL, WIDTH,FREQ,FREQ_CAP) \
Myles Watsond61ada62008-10-02 19:20:22 +0000179 (((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
Jason Schildt6e44b422005-08-09 21:53:07 +0000180
Jason Schildt043b4092005-08-10 15:16:44 +0000181#define LINK_CTRL(OFFS) ((OFFS >> 24) & 0xFF)
Eric Biederman5cd81732004-03-11 15:01:31 +0000182#define LINK_WIDTH(OFFS) ((OFFS >> 16) & 0xFF)
Jason Schildt043b4092005-08-10 15:16:44 +0000183#define LINK_FREQ(OFFS) ((OFFS >> 8) & 0xFF)
Eric Biederman5cd81732004-03-11 15:01:31 +0000184#define LINK_FREQ_CAP(OFFS) ((OFFS) & 0xFF)
185
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000186#define PCI_HT_HOST_OFFS LINK_OFFS( \
Myles Watsond61ada62008-10-02 19:20:22 +0000187 PCI_HT_CAP_HOST_CTRL, \
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000188 PCI_HT_CAP_HOST_WIDTH, \
189 PCI_HT_CAP_HOST_FREQ, \
190 PCI_HT_CAP_HOST_FREQ_CAP)
Eric Biederman5cd81732004-03-11 15:01:31 +0000191
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000192#define PCI_HT_SLAVE0_OFFS LINK_OFFS( \
Myles Watsond61ada62008-10-02 19:20:22 +0000193 PCI_HT_CAP_SLAVE_CTRL0, \
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000194 PCI_HT_CAP_SLAVE_WIDTH0, \
195 PCI_HT_CAP_SLAVE_FREQ0, \
196 PCI_HT_CAP_SLAVE_FREQ_CAP0)
Eric Biederman5cd81732004-03-11 15:01:31 +0000197
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000198#define PCI_HT_SLAVE1_OFFS LINK_OFFS( \
Myles Watsond61ada62008-10-02 19:20:22 +0000199 PCI_HT_CAP_SLAVE_CTRL1, \
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000200 PCI_HT_CAP_SLAVE_WIDTH1, \
201 PCI_HT_CAP_SLAVE_FREQ1, \
202 PCI_HT_CAP_SLAVE_FREQ_CAP1)
Eric Biederman5cd81732004-03-11 15:01:31 +0000203
204static int ht_optimize_link(
Jason Schildt043b4092005-08-10 15:16:44 +0000205 device_t dev1, uint8_t pos1, unsigned offs1,
206 device_t dev2, uint8_t pos2, unsigned offs2)
Eric Biederman5cd81732004-03-11 15:01:31 +0000207{
208 static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
209 static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
Jason Schildt043b4092005-08-10 15:16:44 +0000210 uint16_t freq_cap1, freq_cap2;
211 uint8_t width_cap1, width_cap2, width, old_width, ln_width1, ln_width2;
212 uint8_t freq, old_freq;
Eric Biederman5cd81732004-03-11 15:01:31 +0000213 int needs_reset;
214 /* Set link width and frequency */
215
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000216 printk(BIOS_SPEW, "entering ht_optimize_link\n");
Eric Biederman5cd81732004-03-11 15:01:31 +0000217 /* Initially assume everything is already optimized and I don't need a reset */
218 needs_reset = 0;
219
220 /* Get the frequency capabilities */
221 freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1));
222 freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2));
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000223 printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\n", freq_cap1, freq_cap2);
Eric Biederman5cd81732004-03-11 15:01:31 +0000224
225 /* Calculate the highest possible frequency */
226 freq = log2(freq_cap1 & freq_cap2);
227
228 /* See if I am changing the link freqency */
229 old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1));
Jason Schildtcf6df2a2005-10-25 21:41:45 +0000230 old_freq &= 0x0f;
Eric Biederman5cd81732004-03-11 15:01:31 +0000231 needs_reset |= old_freq != freq;
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000232 printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset);
Eric Biederman5cd81732004-03-11 15:01:31 +0000233 old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2));
Jason Schildtcf6df2a2005-10-25 21:41:45 +0000234 old_freq &= 0x0f;
Eric Biederman5cd81732004-03-11 15:01:31 +0000235 needs_reset |= old_freq != freq;
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000236 printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset);
Eric Biederman5cd81732004-03-11 15:01:31 +0000237
Carl-Daniel Hailfingerc589e5a2008-12-23 02:05:55 +0000238 /* Set the Calculated link frequency */
Eric Biederman5cd81732004-03-11 15:01:31 +0000239 pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq);
240 pci_write_config8(dev2, pos2 + LINK_FREQ(offs2), freq);
241
242 /* Get the width capabilities */
Yinghai Lu00a018f2007-04-06 21:06:44 +0000243 width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1));
244 width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2));
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000245 printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\n", width_cap1, width_cap2);
Eric Biederman5cd81732004-03-11 15:01:31 +0000246
247 /* Calculate dev1's input width */
248 ln_width1 = link_width_to_pow2[width_cap1 & 7];
249 ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000250 printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2);
Eric Biederman5cd81732004-03-11 15:01:31 +0000251 if (ln_width1 > ln_width2) {
252 ln_width1 = ln_width2;
253 }
254 width = pow2_to_link_width[ln_width1];
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000255 printk(BIOS_SPEW, "dev1 input width=0x%x\n", width);
Eric Biederman5cd81732004-03-11 15:01:31 +0000256 /* Calculate dev1's output width */
257 ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
258 ln_width2 = link_width_to_pow2[width_cap2 & 7];
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000259 printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2);
Eric Biederman5cd81732004-03-11 15:01:31 +0000260 if (ln_width1 > ln_width2) {
261 ln_width1 = ln_width2;
262 }
263 width |= pow2_to_link_width[ln_width1] << 4;
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000264 printk(BIOS_SPEW, "dev1 input|output width=0x%x\n", width);
Eric Biederman5cd81732004-03-11 15:01:31 +0000265
266 /* See if I am changing dev1's width */
267 old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000268 old_width &= 0x77;
Eric Biederman5cd81732004-03-11 15:01:31 +0000269 needs_reset |= old_width != width;
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000270 printk(BIOS_SPEW, "old dev1 input|output width=0x%x\n", width);
Eric Biederman5cd81732004-03-11 15:01:31 +0000271
272 /* Set dev1's widths */
273 pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width);
274
275 /* Calculate dev2's width */
276 width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000277 printk(BIOS_SPEW, "dev2 input|output width=0x%x\n", width);
Eric Biederman5cd81732004-03-11 15:01:31 +0000278
279 /* See if I am changing dev2's width */
280 old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000281 old_width &= 0x77;
Eric Biederman5cd81732004-03-11 15:01:31 +0000282 needs_reset |= old_width != width;
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000283 printk(BIOS_SPEW, "old dev2 input|output width=0x%x\n", width);
Eric Biederman5cd81732004-03-11 15:01:31 +0000284
285 /* Set dev2's widths */
286 pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width);
287
288 return needs_reset;
289}
Myles Watsond61ada62008-10-02 19:20:22 +0000290
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000291#if CONFIG_RAMINIT_SYSINFO
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000292static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo)
293#else
294static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid)
295#endif
Jason Schildt043b4092005-08-10 15:16:44 +0000296{
Stefan Reinauer08670622009-06-30 15:17:49 +0000297 //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000298
Jason Schildt043b4092005-08-10 15:16:44 +0000299 uint8_t next_unitid, last_unitid;
300 unsigned uoffs;
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000301
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000302#if !CONFIG_RAMINIT_SYSINFO
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000303 int reset_needed = 0;
304#endif
305
Stefan Reinauer08670622009-06-30 15:17:49 +0000306#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
307 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
Stefan Reinauer328a6942011-10-13 17:04:02 -0700308 unsigned real_last_unitid = 0;
309 uint8_t real_last_pos = 0;
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000310 int ht_dev_num = 0;
Yinghai Lu18c70d72007-09-14 14:58:33 +0000311 uint8_t end_used = 0;
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000312#endif
Jason Schildt043b4092005-08-10 15:16:44 +0000313
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000314 uoffs = PCI_HT_HOST_OFFS;
Stefan Reinauer08670622009-06-30 15:17:49 +0000315 next_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1;
Yinghai Lu6a61d6a2004-10-20 05:07:16 +0000316
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000317 do {
Jason Schildt043b4092005-08-10 15:16:44 +0000318 uint32_t id;
319 uint8_t pos;
320 uint16_t flags, ctrl;
321 uint8_t count;
322 unsigned offs;
Myles Watsond61ada62008-10-02 19:20:22 +0000323
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000324 /* Wait until the link initialization is complete */
325 do {
326 ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
327 /* Is this the end of the hypertransport chain? */
328 if (ctrl & (1 << 6)) {
Myles Watsond61ada62008-10-02 19:20:22 +0000329 goto end_of_chain;
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000330 }
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000331
332 if (ctrl & ((1 << 4) | (1 << 8))) {
Myles Watsond61ada62008-10-02 19:20:22 +0000333 /*
334 * Either the link has failed, or we have
335 * a CRC error.
336 * Sometimes this can happen due to link
337 * retrain, so lets knock it down and see
338 * if its transient
339 */
Stefan Reinauerfbce0ff2006-04-11 18:36:42 +0000340 ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
Myles Watsond61ada62008-10-02 19:20:22 +0000341 pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl);
342 ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
343 if (ctrl & ((1 << 4) | (1 << 8))) {
344 print_err("Detected error on Hypertransport Link\n");
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000345 break;
Myles Watsond61ada62008-10-02 19:20:22 +0000346 }
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000347 }
348 } while((ctrl & (1 << 5)) == 0);
Myles Watsond61ada62008-10-02 19:20:22 +0000349
Yinghai Lu6a61d6a2004-10-20 05:07:16 +0000350 device_t dev = PCI_DEV(bus, 0, 0);
Jason Schildt043b4092005-08-10 15:16:44 +0000351 last_unitid = next_unitid;
352
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000353 id = pci_read_config32(dev, PCI_VENDOR_ID);
Jason Schildt043b4092005-08-10 15:16:44 +0000354
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000355 /* If the chain is enumerated quit */
Myles Watsond61ada62008-10-02 19:20:22 +0000356 if ((id == 0xffffffff) || (id == 0x00000000) ||
357 (id == 0x0000ffff) || (id == 0xffff0000))
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000358 {
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000359 break;
360 }
Yinghai Lu6a61d6a2004-10-20 05:07:16 +0000361
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000362 pos = ht_lookup_slave_capability(dev);
363 if (!pos) {
Myles Watsond61ada62008-10-02 19:20:22 +0000364 print_err("udev="); print_err_hex32(udev);
365 print_err("\tupos="); print_err_hex32(upos);
366 print_err("\tuoffs="); print_err_hex32(uoffs);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000367 print_err("\tHT link capability not found\n");
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000368 break;
369 }
Yinghai Lu6a61d6a2004-10-20 05:07:16 +0000370
Yinghai Lu00a018f2007-04-06 21:06:44 +0000371
Stefan Reinauer08670622009-06-30 15:17:49 +0000372#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
Yinghai Lu00a018f2007-04-06 21:06:44 +0000373 if(offset_unitid) {
Yinghai Lu18c70d72007-09-14 14:58:33 +0000374 if(next_unitid>= (bus ? 0x20:0x18) ) {
375 if(!end_used) {
Stefan Reinauer08670622009-06-30 15:17:49 +0000376 next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
Yinghai Lu18c70d72007-09-14 14:58:33 +0000377 end_used = 1;
378 } else {
379 goto out;
380 }
Myles Watsond61ada62008-10-02 19:20:22 +0000381
382 }
383 real_last_pos = pos;
Yinghai Lu18c70d72007-09-14 14:58:33 +0000384 real_last_unitid = next_unitid;
Yinghai Lu00a018f2007-04-06 21:06:44 +0000385 ht_dev_num++;
Myles Watsond61ada62008-10-02 19:20:22 +0000386 }
Yinghai Lu00a018f2007-04-06 21:06:44 +0000387#endif
Yinghai Lu18c70d72007-09-14 14:58:33 +0000388 /* Update the Unitid of the current device */
389 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
390 flags &= ~0x1f; /* mask out the base Unit ID */
391 flags |= next_unitid & 0x1f;
arch import user (historical)98d0d302005-07-06 17:13:46 +0000392 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
393
Myles Watsond61ada62008-10-02 19:20:22 +0000394 /* Compute the number of unitids consumed */
395 count = (flags >> 5) & 0x1f;
Yinghai Lu18c70d72007-09-14 14:58:33 +0000396
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000397 /* Note the change in device number */
Yinghai Lu18c70d72007-09-14 14:58:33 +0000398 dev = PCI_DEV(bus, next_unitid, 0);
Yinghai Lue3247312005-01-20 20:41:17 +0000399
Myles Watsond61ada62008-10-02 19:20:22 +0000400 next_unitid += count;
Yinghai Lue3247312005-01-20 20:41:17 +0000401
Yinghai Lud4b278c2006-10-04 20:46:15 +0000402 /* Find which side of the ht link we are on,
403 * by reading which direction our last write to PCI_CAP_FLAGS
404 * came from.
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000405 */
406 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
Myles Watsond61ada62008-10-02 19:20:22 +0000407 offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
408
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000409 #if CONFIG_RAMINIT_SYSINFO
Myles Watsond61ada62008-10-02 19:20:22 +0000410 /* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000411 {
412 struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num];
413 link_pair->udev = udev;
414 link_pair->upos = upos;
415 link_pair->uoffs = uoffs;
416 link_pair->dev = dev;
417 link_pair->pos = pos;
418 link_pair->offs = offs;
419 sysinfo->link_pair_num++;
420 }
421 #else
422 reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, offs);
423 #endif
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000424
Yinghai Lud4b278c2006-10-04 20:46:15 +0000425 /* Remeber the location of the last device */
arch import user (historical)98d0d302005-07-06 17:13:46 +0000426 udev = dev;
427 upos = pos;
428 uoffs = ( offs != PCI_HT_SLAVE0_OFFS ) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS;
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000429
Yinghai Lu18c70d72007-09-14 14:58:33 +0000430 } while (last_unitid != next_unitid );
Jason Schildt043b4092005-08-10 15:16:44 +0000431
Stefan Reinauer08670622009-06-30 15:17:49 +0000432#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
Yinghai Lu18c70d72007-09-14 14:58:33 +0000433out:
Myles Watsonfa12b672009-04-30 22:45:41 +0000434#endif
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000435end_of_chain: ;
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000436
Stefan Reinauer08670622009-06-30 15:17:49 +0000437#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
438 if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) {
Myles Watsond61ada62008-10-02 19:20:22 +0000439 uint16_t flags;
Myles Watsond61ada62008-10-02 19:20:22 +0000440 flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
441 flags &= ~0x1f;
Stefan Reinauer08670622009-06-30 15:17:49 +0000442 flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
Myles Watsond61ada62008-10-02 19:20:22 +0000443 pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
444
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000445 #if CONFIG_RAMINIT_SYSINFO
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000446 // Here need to change the dev in the array
Stefan Reinauerc51dc442010-04-07 01:44:04 +0000447 int i;
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000448 for(i=0;i<sysinfo->link_pair_num;i++)
Myles Watsond61ada62008-10-02 19:20:22 +0000449 {
450 struct link_pair_st *link_pair = &sysinfo->link_pair[i];
451 if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) {
Stefan Reinauer08670622009-06-30 15:17:49 +0000452 link_pair->udev = PCI_DEV(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000453 continue;
454 }
Myles Watsond61ada62008-10-02 19:20:22 +0000455 if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) {
Stefan Reinauer08670622009-06-30 15:17:49 +0000456 link_pair->dev = PCI_DEV(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0);
Myles Watsond61ada62008-10-02 19:20:22 +0000457 }
458 }
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000459 #endif
460
Myles Watsond61ada62008-10-02 19:20:22 +0000461 }
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000462#endif
463
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000464#if !CONFIG_RAMINIT_SYSINFO
Yinghai Lu6a61d6a2004-10-20 05:07:16 +0000465 return reset_needed;
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000466#endif
467
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000468}
Li-Ta Loedeff592004-03-25 17:50:06 +0000469
Stefan Reinauerd4f53732010-04-09 14:46:51 +0000470#if 0
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000471#if CONFIG_RAMINIT_SYSINFO
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000472static void ht_setup_chain(device_t udev, unsigned upos, struct sys_info *sysinfo)
473#else
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000474static int ht_setup_chain(device_t udev, unsigned upos)
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000475#endif
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000476{
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000477 unsigned offset_unitid = 0;
Stefan Reinauer08670622009-06-30 15:17:49 +0000478#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
Myles Watsond61ada62008-10-02 19:20:22 +0000479 offset_unitid = 1;
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000480#endif
481
Myles Watsond61ada62008-10-02 19:20:22 +0000482 /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
483 * On most boards this just happens. If a cpu has multiple
484 * non Coherent links the appropriate bus registers for the
485 * links needs to be programed to point at bus 0.
486 */
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000487
Myles Watsond61ada62008-10-02 19:20:22 +0000488 /* Make certain the HT bus is not enumerated */
489 ht_collapse_previous_enumeration(0, 0);
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000490
Stefan Reinauer08670622009-06-30 15:17:49 +0000491#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
Myles Watsond61ada62008-10-02 19:20:22 +0000492 offset_unitid = 1;
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000493#endif
494
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000495#if CONFIG_RAMINIT_SYSINFO
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000496 ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo);
497#else
Myles Watsond61ada62008-10-02 19:20:22 +0000498 return ht_setup_chainx(udev, upos, 0, offset_unitid);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000499#endif
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000500}
Stefan Reinauerd4f53732010-04-09 14:46:51 +0000501#endif
502
Yinghai Lud4b278c2006-10-04 20:46:15 +0000503static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val)
Yinghai Lu1bc56542005-01-06 02:23:31 +0000504{
Jason Schildt043b4092005-08-10 15:16:44 +0000505 uint32_t dword, dword_old;
506 uint8_t link_type;
Myles Watsond61ada62008-10-02 19:20:22 +0000507
Yinghai Lu1bc56542005-01-06 02:23:31 +0000508 /* This works on an Athlon64 because unimplemented links return 0 */
509 dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20));
510 link_type = dword & 0xff;
Myles Watsond61ada62008-10-02 19:20:22 +0000511
512
Yinghai Lud4b278c2006-10-04 20:46:15 +0000513 if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
514 dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc);
Yinghai Lu1bc56542005-01-06 02:23:31 +0000515 dword &= ~( 0xff<<(linkn *8) );
516 dword |= val << (linkn *8);
Myles Watsond61ada62008-10-02 19:20:22 +0000517
Yinghai Lud4b278c2006-10-04 20:46:15 +0000518 if (dword != dword_old) {
519 pci_write_config32(PCI_DEV(0,0x18+node,3), 0xdc, dword);
520 return 1;
521 }
Yinghai Lu1bc56542005-01-06 02:23:31 +0000522 }
Myles Watsond61ada62008-10-02 19:20:22 +0000523
Yinghai Lu1bc56542005-01-06 02:23:31 +0000524 return 0;
525}
526
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000527static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
Yinghai Lu1bc56542005-01-06 02:23:31 +0000528{
Myles Watsond61ada62008-10-02 19:20:22 +0000529 int reset_needed;
Jason Schildt043b4092005-08-10 15:16:44 +0000530 uint8_t i;
Yinghai Lu1bc56542005-01-06 02:23:31 +0000531
532 reset_needed = 0;
533
534 for (i = 0; i < ht_c_num; i++) {
Jason Schildt043b4092005-08-10 15:16:44 +0000535 uint32_t reg;
536 uint8_t nodeid, linkn;
537 uint8_t busn;
538 uint8_t val;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000539 unsigned devn = 1;
540
Stefan Reinauer08670622009-06-30 15:17:49 +0000541 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
542 #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
Myles Watsond61ada62008-10-02 19:20:22 +0000543 if(i==0) // to check if it is sb ht chain
544 #endif
Stefan Reinauer08670622009-06-30 15:17:49 +0000545 devn = CONFIG_HT_CHAIN_UNITID_BASE;
Myles Watsond61ada62008-10-02 19:20:22 +0000546 #endif
Yinghai Lu1bc56542005-01-06 02:23:31 +0000547
548 reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
Myles Watsond61ada62008-10-02 19:20:22 +0000549
Yinghai Lu1bc56542005-01-06 02:23:31 +0000550 nodeid = ((reg & 0xf0)>>4); // nodeid
551 linkn = ((reg & 0xf00)>>8); // link n
552 busn = (reg & 0xff0000)>>16; //busn
Yinghai Lud4b278c2006-10-04 20:46:15 +0000553
554 reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted
Yinghai Lu1bc56542005-01-06 02:23:31 +0000555 if ( (reg & 0xffff) == PCI_VENDOR_ID_AMD) {
556 val = 0x25;
Jason Schildt043b4092005-08-10 15:16:44 +0000557 } else if ( (reg & 0xffff) == PCI_VENDOR_ID_NVIDIA ) {
Yinghai Lu1bc56542005-01-06 02:23:31 +0000558 val = 0x25;//???
Jason Schildt043b4092005-08-10 15:16:44 +0000559 } else {
Yinghai Lu1bc56542005-01-06 02:23:31 +0000560 continue;
561 }
562
563 reset_needed |= optimize_link_read_pointer(nodeid, linkn, 0x07, val);
564
565 }
566
567 return reset_needed;
568}
569
Stefan Reinauer432461e2011-04-19 00:36:39 +0000570#if CONFIG_SOUTHBRIDGE_NVIDIA_CK804 // || CONFIG_SOUTHBRIDGE_NVIDIA_MCP55
Yinghai Lud4b278c2006-10-04 20:46:15 +0000571static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
572{
Myles Watsond61ada62008-10-02 19:20:22 +0000573 uint32_t dword;
574 uint8_t link_type;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000575 unsigned regpos;
576 device_t dev;
577
Myles Watsond61ada62008-10-02 19:20:22 +0000578 /* This works on an Athlon64 because unimplemented links return 0 */
Yinghai Lud4b278c2006-10-04 20:46:15 +0000579 regpos = 0x98 + (linkn * 0x20);
580 dev = PCI_DEV(0,0x18+node,0);
Myles Watsond61ada62008-10-02 19:20:22 +0000581 dword = pci_read_config32(dev, regpos);
582 link_type = dword & 0xff;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000583
Myles Watsond61ada62008-10-02 19:20:22 +0000584 if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
Yinghai Lud4b278c2006-10-04 20:46:15 +0000585 regpos = 0x90 + (linkn * 0x20);
Myles Watsond61ada62008-10-02 19:20:22 +0000586 dword = pci_read_config32(dev, regpos );
Yinghai Lud4b278c2006-10-04 20:46:15 +0000587
Myles Watsond61ada62008-10-02 19:20:22 +0000588 if (dword != val) {
589 pci_write_config32(dev, regpos, val);
590 return 1;
591 }
Yinghai Lud4b278c2006-10-04 20:46:15 +0000592 }
593
Myles Watsond61ada62008-10-02 19:20:22 +0000594 return 0;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000595}
Stefan Reinauer116ec612010-04-23 19:16:30 +0000596
Yinghai Lud4b278c2006-10-04 20:46:15 +0000597static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val)
598{
Myles Watsond61ada62008-10-02 19:20:22 +0000599 int reset_needed;
600 uint8_t i;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000601
Myles Watsond61ada62008-10-02 19:20:22 +0000602 reset_needed = 0;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000603
Myles Watsond61ada62008-10-02 19:20:22 +0000604 for (i = 0; i < ht_c_num; i++) {
605 uint32_t reg;
606 uint8_t nodeid, linkn;
607 uint8_t busn;
608 unsigned devn;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000609
Myles Watsond61ada62008-10-02 19:20:22 +0000610 reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
611 if((reg & 3) != 3) continue; // not enabled
Yinghai Lud4b278c2006-10-04 20:46:15 +0000612
Myles Watsond61ada62008-10-02 19:20:22 +0000613 nodeid = ((reg & 0xf0)>>4); // nodeid
614 linkn = ((reg & 0xf00)>>8); // link n
615 busn = (reg & 0xff0000)>>16; //busn
Yinghai Lud4b278c2006-10-04 20:46:15 +0000616
Yinghai Lu00a018f2007-04-06 21:06:44 +0000617 for(devn = 0; devn < 0x20; devn++) {
Myles Watsond61ada62008-10-02 19:20:22 +0000618 reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
619 if ( (reg & 0xffff) == vendorid ) {
620 reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
Yinghai Lu00a018f2007-04-06 21:06:44 +0000621 break;
Myles Watsond61ada62008-10-02 19:20:22 +0000622 }
Yinghai Lu00a018f2007-04-06 21:06:44 +0000623 }
Myles Watsond61ada62008-10-02 19:20:22 +0000624 }
Yinghai Lud4b278c2006-10-04 20:46:15 +0000625
Myles Watsond61ada62008-10-02 19:20:22 +0000626 return reset_needed;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000627}
Stefan Reinauer116ec612010-04-23 19:16:30 +0000628#endif
Yinghai Lud4b278c2006-10-04 20:46:15 +0000629
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000630#if CONFIG_RAMINIT_SYSINFO
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000631static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo)
632#else
Jason Schildt043b4092005-08-10 15:16:44 +0000633static int ht_setup_chains(uint8_t ht_c_num)
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000634#endif
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000635{
Myles Watsond61ada62008-10-02 19:20:22 +0000636 /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
Yinghai Lud4b278c2006-10-04 20:46:15 +0000637 * On most boards this just happens. If a cpu has multiple
638 * non Coherent links the appropriate bus registers for the
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000639 * links needs to be programed to point at bus 0.
640 */
Myles Watsond61ada62008-10-02 19:20:22 +0000641 uint8_t upos;
642 device_t udev;
Jason Schildt043b4092005-08-10 15:16:44 +0000643 uint8_t i;
Li-Ta Loedeff592004-03-25 17:50:06 +0000644
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000645#if !CONFIG_RAMINIT_SYSINFO
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000646 int reset_needed = 0;
647#else
648 sysinfo->link_pair_num = 0;
649#endif
Li-Ta Loedeff592004-03-25 17:50:06 +0000650
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000651 // first one is SB Chain
Li-Ta Lo8e79fc32004-04-15 17:33:21 +0000652 for (i = 0; i < ht_c_num; i++) {
Jason Schildt043b4092005-08-10 15:16:44 +0000653 uint32_t reg;
654 uint8_t devpos;
Yinghai Lu6a61d6a2004-10-20 05:07:16 +0000655 unsigned regpos;
Jason Schildt043b4092005-08-10 15:16:44 +0000656 uint32_t dword;
657 uint8_t busn;
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000658 unsigned offset_unitid = 0;
Myles Watsond61ada62008-10-02 19:20:22 +0000659
Yinghai Lu2c956bb2004-12-17 21:08:16 +0000660 reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
Li-Ta Loedeff592004-03-25 17:50:06 +0000661
Yinghai Lud4b278c2006-10-04 20:46:15 +0000662 //We need setup 0x94, 0xb4, and 0xd4 according to the reg
663 devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19
664 regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4;
Yinghai Lu6a61d6a2004-10-20 05:07:16 +0000665 busn = (reg & 0xff0000)>>16;
Myles Watsond61ada62008-10-02 19:20:22 +0000666
Yinghai Lu6a61d6a2004-10-20 05:07:16 +0000667 dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ;
668 dword &= ~(0xffff<<8);
669 dword |= (reg & 0xffff0000)>>8;
670 pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword);
Myles Watsond61ada62008-10-02 19:20:22 +0000671
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000672
Stefan Reinauer08670622009-06-30 15:17:49 +0000673 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
674 #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
Myles Watsond61ada62008-10-02 19:20:22 +0000675 if(i==0) // to check if it is sb ht chain
676 #endif
677 offset_unitid = 1;
678 #endif
679
680 /* Make certain the HT bus is not enumerated */
681 ht_collapse_previous_enumeration(busn, offset_unitid);
Li-Ta Loedeff592004-03-25 17:50:06 +0000682
Yinghai Lu4403f602004-11-03 00:47:40 +0000683 upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;
Jason Schildt043b4092005-08-10 15:16:44 +0000684 udev = PCI_DEV(0, devpos, 0);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000685
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000686#if CONFIG_RAMINIT_SYSINFO
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000687 ht_setup_chainx(udev,upos,busn, offset_unitid, sysinfo); // all not
688#else
689 reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unitid); //all not
690#endif
Jason Schildt043b4092005-08-10 15:16:44 +0000691
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000692 }
Li-Ta Loedeff592004-03-25 17:50:06 +0000693
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000694#if !CONFIG_RAMINIT_SYSINFO
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000695 reset_needed |= optimize_link_read_pointers_chain(ht_c_num);
Yinghai Lu2c956bb2004-12-17 21:08:16 +0000696
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000697 return reset_needed;
Jason Schildt043b4092005-08-10 15:16:44 +0000698#endif
Yinghai Lu1bc56542005-01-06 02:23:31 +0000699
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000700}
701
Yinghai Lud4b278c2006-10-04 20:46:15 +0000702#if defined (__GNUC__)
703static inline unsigned get_nodes(void);
704#endif
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000705
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000706#if CONFIG_RAMINIT_SYSINFO
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000707static void ht_setup_chains_x(struct sys_info *sysinfo)
708#else
Jason Schildt043b4092005-08-10 15:16:44 +0000709static int ht_setup_chains_x(void)
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000710#endif
Myles Watsond61ada62008-10-02 19:20:22 +0000711{
712 uint8_t nodeid;
713 uint32_t reg;
Jason Schildt043b4092005-08-10 15:16:44 +0000714 uint32_t tempreg;
Myles Watsond61ada62008-10-02 19:20:22 +0000715 uint8_t next_busn;
716 uint8_t ht_c_num;
Jason Schildt043b4092005-08-10 15:16:44 +0000717 uint8_t nodes;
Patrick Georgi7bbd7f22010-11-07 18:20:51 +0000718#if CONFIG_K8_ALLOCATE_IO_RANGE
Jason Schildt043b4092005-08-10 15:16:44 +0000719 unsigned next_io_base;
720#endif
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000721
Myles Watsond61ada62008-10-02 19:20:22 +0000722 nodes = get_nodes();
723
724 /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
725 reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
726 /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
Jason Schildt043b4092005-08-10 15:16:44 +0000727 print_linkn_in("SBLink=", ((reg>>8) & 3) );
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000728#if CONFIG_RAMINIT_SYSINFO
Yinghai Lud4b278c2006-10-04 20:46:15 +0000729 sysinfo->sblk = (reg>>8) & 3;
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000730 sysinfo->sbbusn = 0;
731 sysinfo->nodes = nodes;
732#endif
Myles Watsond61ada62008-10-02 19:20:22 +0000733 tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
734 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg);
Jason Schildt043b4092005-08-10 15:16:44 +0000735
Yinghai Lud4b278c2006-10-04 20:46:15 +0000736 next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
Jason Schildt043b4092005-08-10 15:16:44 +0000737
Patrick Georgi7bbd7f22010-11-07 18:20:51 +0000738#if CONFIG_K8_ALLOCATE_IO_RANGE
Jason Schildt043b4092005-08-10 15:16:44 +0000739 /* io range allocation */
740 tempreg = 0 | (((reg>>8) & 0x3) << 4 )| (0x3<<12); //limit
741 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg);
742 tempreg = 3 | ( 3<<4) | (0<<12); //base
743 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0, tempreg);
744 next_io_base = 0x3+0x1;
745#endif
746
Yinghai Lu1bc56542005-01-06 02:23:31 +0000747 /* clean others */
Myles Watsond61ada62008-10-02 19:20:22 +0000748 for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
749 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
Yinghai Lud4b278c2006-10-04 20:46:15 +0000750
Patrick Georgi7bbd7f22010-11-07 18:20:51 +0000751#if CONFIG_K8_ALLOCATE_IO_RANGE
Jason Schildt043b4092005-08-10 15:16:44 +0000752 /* io range allocation */
753 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);
754 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);
Yinghai Lud4b278c2006-10-04 20:46:15 +0000755#endif
Myles Watsond61ada62008-10-02 19:20:22 +0000756 }
757
758 for(nodeid=0; nodeid<nodes; nodeid++) {
759 device_t dev;
760 uint8_t linkn;
761 dev = PCI_DEV(0, 0x18+nodeid,0);
762 for(linkn = 0; linkn<3; linkn++) {
763 unsigned regpos;
764 regpos = 0x98 + 0x20 * linkn;
765 reg = pci_read_config32(dev, regpos);
766 if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/
Yinghai Lud4b278c2006-10-04 20:46:15 +0000767 print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf));
Myles Watsond61ada62008-10-02 19:20:22 +0000768 tempreg = 3 | (nodeid <<4) | (linkn<<8);
769 /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
770 for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
771 reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
772 if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/
773 break;
774 }
775 }
776 if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/
777 /*update to 0xe0...*/
Yinghai Lud4b278c2006-10-04 20:46:15 +0000778 if((reg & 0xf) == 3) continue; /*SbLink so don't touch it */
Yinghai Lu1bc56542005-01-06 02:23:31 +0000779 print_linkn_in("\tbusn=", next_busn);
Myles Watsond61ada62008-10-02 19:20:22 +0000780 tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24);
781 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
Jason Schildt043b4092005-08-10 15:16:44 +0000782 next_busn+=0x3f+1;
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000783
Patrick Georgi7bbd7f22010-11-07 18:20:51 +0000784#if CONFIG_K8_ALLOCATE_IO_RANGE
Jason Schildt043b4092005-08-10 15:16:44 +0000785 /* io range allocation */
Myles Watsond61ada62008-10-02 19:20:22 +0000786 tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
787 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
788 tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ?
789 pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);
790 next_io_base += 0x3+0x1;
Jason Schildt043b4092005-08-10 15:16:44 +0000791#endif
Yinghai Lud4b278c2006-10-04 20:46:15 +0000792
Myles Watsond61ada62008-10-02 19:20:22 +0000793 }
794 }
795 /*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
Jason Schildt043b4092005-08-10 15:16:44 +0000796
Myles Watsond61ada62008-10-02 19:20:22 +0000797 for(nodeid = 1; nodeid<nodes; nodeid++) {
798 int i;
799 device_t dev;
800 dev = PCI_DEV(0, 0x18+nodeid,1);
801 for(i = 0; i< 4; i++) {
802 unsigned regpos;
803 regpos = 0xe0 + i * 4;
804 reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
805 pci_write_config32(dev, regpos, reg);
806 }
Jason Schildt043b4092005-08-10 15:16:44 +0000807
Patrick Georgi7bbd7f22010-11-07 18:20:51 +0000808#if CONFIG_K8_ALLOCATE_IO_RANGE
Jason Schildt043b4092005-08-10 15:16:44 +0000809 /* io range allocation */
Myles Watsond61ada62008-10-02 19:20:22 +0000810 for(i = 0; i< 4; i++) {
811 unsigned regpos;
812 regpos = 0xc4 + i * 8;
813 reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
814 pci_write_config32(dev, regpos, reg);
815 }
816 for(i = 0; i< 4; i++) {
817 unsigned regpos;
818 regpos = 0xc0 + i * 8;
819 reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
820 pci_write_config32(dev, regpos, reg);
821 }
Jason Schildt043b4092005-08-10 15:16:44 +0000822#endif
Myles Watsond61ada62008-10-02 19:20:22 +0000823 }
824
Yinghai Lu1bc56542005-01-06 02:23:31 +0000825 /* recount ht_c_num*/
Jason Schildt043b4092005-08-10 15:16:44 +0000826 uint8_t i=0;
Myles Watsond61ada62008-10-02 19:20:22 +0000827 for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
Yinghai Lu2c956bb2004-12-17 21:08:16 +0000828 reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
Myles Watsond61ada62008-10-02 19:20:22 +0000829 if(((reg & 0xf) != 0x0)) {
Yinghai Lu2c956bb2004-12-17 21:08:16 +0000830 i++;
831 }
Myles Watsond61ada62008-10-02 19:20:22 +0000832 }
Yinghai Lu2c956bb2004-12-17 21:08:16 +0000833
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000834#if CONFIG_RAMINIT_SYSINFO
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000835 sysinfo->ht_c_num = i;
Myles Watsond61ada62008-10-02 19:20:22 +0000836 ht_setup_chains(i, sysinfo);
Yinghai Lud4b278c2006-10-04 20:46:15 +0000837 sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000838#else
839 return ht_setup_chains(i);
840#endif
Yinghai Lu2c956bb2004-12-17 21:08:16 +0000841
842}
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000843
Jonathan Kollasche5b75072010-10-07 23:02:06 +0000844#if CONFIG_RAMINIT_SYSINFO
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000845static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
846{
Yinghai Lud4b278c2006-10-04 20:46:15 +0000847 // We need to use recorded link pair info to optimize the link
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000848 int i;
849 int reset_needed = 0;
Myles Watsond61ada62008-10-02 19:20:22 +0000850
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000851 unsigned link_pair_num = sysinfo->link_pair_num;
852
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000853 printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n");
854 printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num);
Myles Watsond61ada62008-10-02 19:20:22 +0000855 for(i=0; i< link_pair_num; i++) {
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000856 struct link_pair_st *link_pair= &sysinfo->link_pair[i];
Yinghai Lud4b278c2006-10-04 20:46:15 +0000857 reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000858 printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000859 }
860
Yinghai Lud4b278c2006-10-04 20:46:15 +0000861 reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000862 printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\n", reset_needed);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000863
864 return reset_needed;
865
866}
867#endif
868
869
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000870