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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -05004## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Stefan Reinauer16f515a2010-01-20 18:44:30 +00005## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00006##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00007## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
Patrick Georgi0588d192009-08-12 15:00:51 +000016
Uwe Hermannad8c95f2012-04-12 22:00:03 +020017mainmenu "coreboot configuration"
Patrick Georgi0588d192009-08-12 15:00:51 +000018
Uwe Hermannc04be932009-10-05 13:55:28 +000019menu "General setup"
20
21config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000022 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000023 help
24 Append an extra string to the end of the coreboot version.
25
Uwe Hermann168b11b2009-10-07 16:15:40 +000026 This can be useful if, for instance, you want to append the
27 respective board's hostname or some other identifying string to
28 the coreboot version number, so that you can easily distinguish
29 boot logs of different boards from each other.
30
Patrick Georgi4b8a2412010-02-09 19:35:16 +000031config CBFS_PREFIX
32 string "CBFS prefix to use"
33 default "fallback"
34 help
35 Select the prefix to all files put into the image. It's "fallback"
36 by default, "normal" is a common alternative.
37
Patrick Georgi23d89cc2010-03-16 01:17:19 +000038choice
Uwe Hermannad8c95f2012-04-12 22:00:03 +020039 prompt "Compiler to use"
Patrick Georgi23d89cc2010-03-16 01:17:19 +000040 default COMPILER_GCC
41 help
42 This option allows you to select the compiler used for building
43 coreboot.
Martin Rotha5a628e82016-01-19 12:01:09 -070044 You must build the coreboot crosscompiler for the board that you
45 have selected.
46
47 To build all the GCC crosscompilers (takes a LONG time), run:
48 make crossgcc
49
50 For help on individual architectures, run the command:
51 make help_toolchain
Patrick Georgi23d89cc2010-03-16 01:17:19 +000052
53config COMPILER_GCC
54 bool "GCC"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020055 help
56 Use the GNU Compiler Collection (GCC) to build coreboot.
57
58 For details see http://gcc.gnu.org.
59
Patrick Georgi23d89cc2010-03-16 01:17:19 +000060config COMPILER_LLVM_CLANG
Martin Rotha5a628e82016-01-19 12:01:09 -070061 bool "LLVM/clang (TESTING ONLY - Not currently working)"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020062 help
Martin Rotha5a628e82016-01-19 12:01:09 -070063 Use LLVM/clang to build coreboot. To use this, you must build the
64 coreboot version of the clang compiler. Run the command
65 make clang
66 Note that this option is not currently working correctly and should
67 really only be selected if you're trying to work on getting clang
68 operational.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020069
70 For details see http://clang.llvm.org.
71
Patrick Georgi23d89cc2010-03-16 01:17:19 +000072endchoice
73
Patrick Georgi9b0de712013-12-29 18:45:23 +010074config ANY_TOOLCHAIN
75 bool "Allow building with any toolchain"
76 default n
77 depends on COMPILER_GCC
78 help
79 Many toolchains break when building coreboot since it uses quite
80 unusual linker features. Unless developers explicitely request it,
81 we'll have to assume that they use their distro compiler by mistake.
82 Make sure that using patched compilers is a conscious decision.
83
Patrick Georgi516a2a72010-03-25 21:45:25 +000084config CCACHE
Uwe Hermannad8c95f2012-04-12 22:00:03 +020085 bool "Use ccache to speed up (re)compilation"
Patrick Georgi516a2a72010-03-25 21:45:25 +000086 default n
87 help
88 Enables the use of ccache for faster builds.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020089
90 Requires the ccache utility in your system $PATH.
91
92 For details see https://ccache.samba.org.
Patrick Georgi516a2a72010-03-25 21:45:25 +000093
Sol Boucher69b88bf2015-02-26 11:47:19 -080094config FMD_GENPARSER
95 bool "Generate flashmap descriptor parser using flex and bison"
96 default n
Sol Boucher69b88bf2015-02-26 11:47:19 -080097 help
98 Enable this option if you are working on the flashmap descriptor
99 parser and made changes to fmd_scanner.l or fmd_parser.y.
100
101 Otherwise, say N to use the provided pregenerated scanner/parser.
102
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000103config SCONFIG_GENPARSER
104 bool "Generate SCONFIG parser using flex and bison"
105 default n
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000106 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200107 Enable this option if you are working on the sconfig device tree
Sol Boucher69b88bf2015-02-26 11:47:19 -0800108 parser and made changes to sconfig.l or sconfig.y.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200109
Sol Boucher69b88bf2015-02-26 11:47:19 -0800110 Otherwise, say N to use the provided pregenerated scanner/parser.
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000111
Joe Korty6d772522010-05-19 18:41:15 +0000112config USE_OPTION_TABLE
113 bool "Use CMOS for configuration values"
114 default n
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000115 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +0000116 help
117 Enable this option if coreboot shall read options from the "CMOS"
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200118 NVRAM instead of using hard-coded values.
Joe Korty6d772522010-05-19 18:41:15 +0000119
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600120config STATIC_OPTION_TABLE
121 bool "Load default configuration values into CMOS on each boot"
122 default n
123 depends on USE_OPTION_TABLE
124 help
125 Enable this option to reset "CMOS" NVRAM values to default on
126 every boot. Use this if you want the NVRAM configuration to
127 never be modified from its default values.
128
Julius Wernercdf92ea2014-12-09 12:18:00 -0800129config UNCOMPRESSED_RAMSTAGE
130 bool
131 default n
132
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000133config COMPRESS_RAMSTAGE
134 bool "Compress ramstage with LZMA"
Julius Wernercdf92ea2014-12-09 12:18:00 -0800135 default y if !UNCOMPRESSED_RAMSTAGE
136 default n
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000137 help
138 Compress ramstage to save memory in the flash image. Note
139 that decompression might slow down booting if the boot flash
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200140 is connected through a slow link (i.e. SPI).
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000141
Julius Werner09f29212015-09-29 13:51:35 -0700142config COMPRESS_PRERAM_STAGES
143 bool "Compress romstage and verstage with LZ4"
Martin Rothf2e04612016-03-09 15:50:23 -0700144 depends on !ARCH_X86
145 default y
Julius Werner09f29212015-09-29 13:51:35 -0700146 help
147 Compress romstage and (if it exists) verstage with LZ4 to save flash
148 space and speed up boot, since the time for reading the image from SPI
149 (and in the vboot case verifying it) is usually much greater than the
150 time spent decompressing. Doesn't work for XIP stages (assume all
151 ARCH_X86 for now) for obvious reasons.
152
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200153config INCLUDE_CONFIG_FILE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200154 bool "Include the coreboot .config file into the ROM image"
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200155 default y
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200156 help
157 Include the .config file that was used to compile coreboot
158 in the (CBFS) ROM image. This is useful if you want to know which
159 options were used to build a specific coreboot.rom image.
160
Daniele Forsi53847a22014-07-22 18:00:56 +0200161 Saying Y here will increase the image size by 2-3KB.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200162
163 You can use the following command to easily list the options:
164
165 grep -a CONFIG_ coreboot.rom
166
167 Alternatively, you can also use cbfstool to print the image
168 contents (including the raw 'config' item we're looking for).
169
170 Example:
171
172 $ cbfstool coreboot.rom print
173 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
174 offset 0x0
175 Alignment: 64 bytes
Steve Goodrichf0269122012-05-18 11:18:47 -0600176
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200177 Name Offset Type Size
178 cmos_layout.bin 0x0 cmos layout 1159
179 fallback/romstage 0x4c0 stage 339756
Daniele Forsi53847a22014-07-22 18:00:56 +0200180 fallback/ramstage 0x53440 stage 186664
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200181 fallback/payload 0x80dc0 payload 51526
182 config 0x8d740 raw 3324
183 (empty) 0x8e480 null 3610440
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200184
Furquan Shaikh94b18a12016-05-04 23:25:16 -0700185config NO_XIP_EARLY_STAGES
186 bool
187 default n if ARCH_X86
188 default y
189 help
Furquan Shaikhd5583a52016-06-01 01:53:18 -0700190 Identify if early stages are eXecute-In-Place(XIP).
Furquan Shaikh94b18a12016-05-04 23:25:16 -0700191
Kyösti Mälkkif8bf5a12013-10-11 22:08:02 +0300192config EARLY_CBMEM_INIT
Kyösti Mälkki3bf38542014-12-18 22:22:04 +0200193 def_bool !LATE_CBMEM_INIT
194
Lee Leahye2422e32016-07-24 19:52:15 -0700195config EARLY_CBMEM_LIST
196 bool
197 default n
198 help
199 Enable display of CBMEM during romstage and postcar.
200
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700201config COLLECT_TIMESTAMPS
202 bool "Create a table of timestamps collected during boot"
Kyösti Mälkki26447932013-10-11 21:14:59 +0300203 default n
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700204 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200205 Make coreboot create a table of timer-ID/timer-value pairs to
206 allow measuring time spent at different phases of the boot process.
207
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200208config USE_BLOBS
209 bool "Allow use of binary-only repository"
210 default n
211 help
212 This draws in the blobs repository, which contains binary files that
213 might be required for some chipsets or boards.
214 This flag ensures that a "Free" option remains available for users.
215
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800216config COVERAGE
217 bool "Code coverage support"
218 depends on COMPILER_GCC
219 default n
220 help
221 Add code coverage support for coreboot. This will store code
222 coverage information in CBMEM for extraction from user space.
223 If unsure, say N.
224
Stefan Reinauer58470e32014-10-17 13:08:36 +0200225config RELOCATABLE_MODULES
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200226 bool
Stefan Reinauer58470e32014-10-17 13:08:36 +0200227 default n
228 help
229 If RELOCATABLE_MODULES is selected then support is enabled for
230 building relocatable modules in the RAM stage. Those modules can be
231 loaded anywhere and all the relocations are handled automatically.
232
233config RELOCATABLE_RAMSTAGE
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200234 depends on EARLY_CBMEM_INIT
Stefan Reinauer58470e32014-10-17 13:08:36 +0200235 bool "Build the ramstage to be relocatable in 32-bit address space."
236 default n
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200237 select RELOCATABLE_MODULES
Stefan Reinauer58470e32014-10-17 13:08:36 +0200238 help
239 The reloctable ramstage support allows for the ramstage to be built
240 as a relocatable module. The stage loader can identify a place
241 out of the OS way so that copying memory is unnecessary during an S3
242 wake. When selecting this option the romstage is responsible for
243 determing a stack location to use for loading the ramstage.
244
245config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
246 depends on RELOCATABLE_RAMSTAGE
247 bool "Cache the relocated ramstage outside of cbmem."
248 default n
249 help
250 The relocated ramstage is saved in an area specified by the
251 by the board and/or chipset.
252
Furquan Shaikh1e162bf2016-05-06 09:20:35 -0700253config NO_STAGE_CACHE
254 bool
255 default n
256 help
257 Do not save any component in stage cache for resume path. On resume,
258 all components would be read back from CBFS again.
259
Julius Werner86fc11d2015-10-09 13:37:58 -0700260# TODO: This doesn't belong here, move to src/arch/x86/Kconfig
Stefan Reinauer58470e32014-10-17 13:08:36 +0200261choice
262 prompt "Bootblock behaviour"
263 default BOOTBLOCK_SIMPLE
264
265config BOOTBLOCK_SIMPLE
266 bool "Always load fallback"
267
268config BOOTBLOCK_NORMAL
269 bool "Switch to normal if CMOS says so"
270
271endchoice
272
Julius Werner86fc11d2015-10-09 13:37:58 -0700273# To be selected by arch, SoC or mainboard if it does not want use the normal
274# src/lib/bootblock.c#main() C entry point.
275config BOOTBLOCK_CUSTOM
276 bool
277 default n
278
Stefan Reinauer58470e32014-10-17 13:08:36 +0200279config BOOTBLOCK_SOURCE
280 string
281 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
282 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
283
Alexandru Gagniucee464b12015-10-02 18:01:18 -0700284# To be selected by arch or platform if a C environment is available during the
285# bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
286config C_ENVIRONMENT_BOOTBLOCK
Martin Roth95f33f4e2016-01-21 12:30:52 -0700287 bool
288 default n
Alexandru Gagniucee464b12015-10-02 18:01:18 -0700289
Timothy Pearson44724082015-03-16 11:47:45 -0500290config SKIP_MAX_REBOOT_CNT_CLEAR
291 bool "Do not clear reboot count after successful boot"
292 default n
Timothy Pearson3bfd7cc2015-11-01 02:13:17 -0600293 depends on BOOTBLOCK_NORMAL
Timothy Pearson44724082015-03-16 11:47:45 -0500294 help
295 Do not clear the reboot count immediately after successful boot.
296 Set to allow the payload to control normal/fallback image recovery.
Timothy Pearson3bfd7cc2015-11-01 02:13:17 -0600297 Note that it is the responsibility of the payload to reset the
298 normal boot bit to 1 after each successsful boot.
Timothy Pearson44724082015-03-16 11:47:45 -0500299
Stefan Reinauer58470e32014-10-17 13:08:36 +0200300config UPDATE_IMAGE
301 bool "Update existing coreboot.rom image"
302 default n
303 help
304 If this option is enabled, no new coreboot.rom file
305 is created. Instead it is expected that there already
306 is a suitable file for further processing.
307 The bootblock will not be modified.
308
Martin Roth5942e062016-01-20 14:59:21 -0700309 If unsure, select 'N'
310
Stefan Reinauerd06258c2015-03-26 16:29:00 -0700311config GENERIC_GPIO_LIB
312 bool
313 default n
314 help
315 If enabled, compile the generic GPIO library. A "generic" GPIO
316 implies configurability usually found on SoCs, particularly the
317 ability to control internal pull resistors.
318
Naresh G Solanki335781a2016-10-26 19:43:14 +0530319config GENERIC_SPD_BIN
320 bool
321 default n
322 help
323 If enabled, add support for adding spd.hex files in cbfs as spd.bin
324 and locating it runtime to load SPD. Additionally provide provision to
325 fetch SPD over SMBus.
326
327config DIMM_MAX
328 int
Barnali Sarkara5b10412016-11-28 14:53:12 +0530329 default 4
Naresh G Solanki335781a2016-10-26 19:43:14 +0530330 depends on GENERIC_SPD_BIN
331 help
332 Total number of memory DIMM slots available on motherboard.
333 It is multiplication of number of channel to number of DIMMs per
334 channel
335
336config DIMM_SPD_SIZE
337 int
338 default 256
339 depends on GENERIC_SPD_BIN
340 help
341 Total SPD size that will be used for DIMM.
342 Ex: DDR3 256, DDR4 512.
343
Stefan Reinauerd06258c2015-03-26 16:29:00 -0700344config BOARD_ID_AUTO
345 bool
346 default n
347 help
348 Mainboards that can read a board ID from the hardware straps
349 (ie. GPIO) select this configuration option.
350
351config BOARD_ID_MANUAL
Vladimir Serbinenko1e161422015-05-30 22:47:22 +0200352 bool
Stefan Reinauerd06258c2015-03-26 16:29:00 -0700353 default n
354 depends on !BOARD_ID_AUTO
355 help
356 If you want to maintain a board ID, but the hardware does not
357 have straps to automatically determine the ID, you can say Y
358 here and add a file named 'board_id' to CBFS. If you don't know
359 what this is about, say N.
360
361config BOARD_ID_STRING
362 string "Board ID"
363 default "(none)"
364 depends on BOARD_ID_MANUAL
365 help
366 This string is placed in the 'board_id' CBFS file for indicating
367 board type.
368
David Hendricks627b3bd2014-11-03 17:42:09 -0800369config RAM_CODE_SUPPORT
Vladimir Serbinenko8ef9c562015-05-30 22:55:44 +0200370 bool
David Hendricks627b3bd2014-11-03 17:42:09 -0800371 default n
372 help
373 If enabled, coreboot discovers RAM configuration (value obtained by
374 reading board straps) and stores it in coreboot table.
375
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400376config BOOTSPLASH_IMAGE
377 bool "Add a bootsplash image"
378 help
379 Select this option if you have a bootsplash image that you would
380 like to add to your ROM.
381
382 This will only add the image to the ROM. To actually run it check
383 options under 'Display' section.
384
385config BOOTSPLASH_FILE
386 string "Bootsplash path and filename"
387 depends on BOOTSPLASH_IMAGE
388 default "bootsplash.jpg"
389 help
390 The path and filename of the file to use as graphical bootsplash
391 screen. The file format has to be jpg.
392
Uwe Hermannc04be932009-10-05 13:55:28 +0000393endmenu
394
Martin Roth026e4dc2015-06-19 23:17:15 -0600395menu "Mainboard"
396
Stefan Reinauera48ca842015-04-04 01:58:28 +0200397source "src/mainboard/Kconfig"
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000398
Marshall Dawsone9375132016-09-04 08:38:33 -0600399config DEVICETREE
400 string
401 default "devicetree.cb"
402 help
403 This symbol allows mainboards to select a different file under their
404 mainboard directory for the devicetree.cb file. This allows the board
405 variants that need different devicetrees to be in the same directory.
406
407 Examples: "devicetree.variant.cb"
408 "variant/devicetree.cb"
409
Martin Roth59ff3402016-02-09 09:06:46 -0700410# defaults for CBFS_SIZE are set at the end of the file.
Martin Roth026e4dc2015-06-19 23:17:15 -0600411config CBFS_SIZE
412 hex "Size of CBFS filesystem in ROM"
Martin Roth026e4dc2015-06-19 23:17:15 -0600413 help
414 This is the part of the ROM actually managed by CBFS, located at the
415 end of the ROM (passed through cbfstool -o) on x86 and at at the start
416 of the ROM (passed through cbfstool -s) everywhere else. It defaults
417 to span the whole ROM on all but Intel systems that use an Intel Firmware
418 Descriptor. It can be overridden to make coreboot live alongside other
419 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
420 binaries.
421
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200422config FMDFILE
423 string "fmap description file in fmd format"
Patrick Georgi5d7ab392015-12-12 00:23:15 +0100424 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200425 default ""
426 help
427 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
428 but in some cases more complex setups are required.
429 When an fmd is specified, it overrides the default format.
430
Vadim Bendebury26588702016-06-02 20:43:19 -0700431config MAINBOARD_HAS_TPM2
432 bool
433 default n
434 help
435 There is a TPM device installed on the mainboard, and it is
436 compliant with version 2 TCG TPM specification. Could be connected
437 over LPC, SPI or I2C.
438
Martin Rothda1ca202015-12-26 16:51:16 -0700439endmenu
440
Martin Rothb09a5692016-01-24 19:38:33 -0700441# load site-local kconfig to allow user specific defaults and overrides
442source "site-local/Kconfig"
443
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200444config SYSTEM_TYPE_LAPTOP
Martin Roth595e7772015-04-26 18:53:26 -0600445 default n
446 bool
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200447
Werner Zehc0fb3612016-01-14 15:08:36 +0100448config CBFS_AUTOGEN_ATTRIBUTES
449 default n
450 bool
451 help
452 If this option is selected, every file in cbfs which has a constraint
453 regarding position or alignment will get an additional file attribute
454 which describes this constraint.
455
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000456menu "Chipset"
457
Duncan Lauried2119762015-06-08 18:11:56 -0700458comment "SoC"
459source "src/soc/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000460comment "CPU"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200461source "src/cpu/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000462comment "Northbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200463source "src/northbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000464comment "Southbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200465source "src/southbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000466comment "Super I/O"
Omar Pakker57603e22016-07-29 23:31:45 +0200467source "src/superio/*/*/Kconfig"
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000468comment "Embedded Controllers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200469source "src/ec/acpi/Kconfig"
470source "src/ec/*/*/Kconfig"
Stefan Reinauer86ddd732016-03-11 20:22:28 -0800471# FIXME move to vendorcode
Marc Jones78687972015-04-22 23:16:31 -0600472source "src/drivers/intel/fsp1_0/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000473
Martin Roth59aa2b12015-06-20 16:17:12 -0600474source "src/southbridge/intel/common/firmware/Kconfig"
Furquan Shaikh2a12e2e2016-07-25 11:48:03 -0700475source "src/vboot/Kconfig"
Martin Rothe1523ec2015-06-19 22:30:43 -0600476source "src/vendorcode/*/Kconfig"
Martin Roth59aa2b12015-06-20 16:17:12 -0600477
Martin Rothe1523ec2015-06-19 22:30:43 -0600478source "src/arch/*/Kconfig"
479
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000480endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000481
Stefan Reinauera48ca842015-04-04 01:58:28 +0200482source "src/device/Kconfig"
Stefan Reinauer95a63962012-11-13 17:00:01 -0800483
Rudolf Marekd9c25492010-05-16 15:31:53 +0000484menu "Generic Drivers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200485source "src/drivers/*/Kconfig"
Stefan Reinauer86ddd732016-03-11 20:22:28 -0800486source "src/drivers/*/*/Kconfig"
Rudolf Marekd9c25492010-05-16 15:31:53 +0000487endmenu
488
Martin Roth09210a12016-05-17 11:28:23 -0600489source "src/acpi/Kconfig"
490
Aaron Durbin4a36c4e2016-08-11 11:02:26 -0500491# This option is for the current boards/chipsets where SPI flash
492# is not the boot device. Currently nearly all boards/chipsets assume
493# SPI flash is the boot device.
494config BOOT_DEVICE_NOT_SPI_FLASH
495 bool
496 default n
497
498config BOOT_DEVICE_SPI_FLASH
499 bool
500 default y if !BOOT_DEVICE_NOT_SPI_FLASH
501 default n
502
Aaron Durbin16c173f2016-08-11 14:04:10 -0500503config BOOT_DEVICE_MEMORY_MAPPED
504 bool
505 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
506 default n
507 help
508 Inform system if SPI is memory-mapped or not.
509
Aaron Durbine8e118d2016-08-12 15:00:10 -0500510config BOOT_DEVICE_SUPPORTS_WRITES
511 bool
512 default n
513 help
514 Indicate that the platform has writable boot device
515 support.
516
Patrick Georgi0770f252015-04-22 13:28:21 +0200517config RTC
518 bool
519 default n
520
Stefan Reinauer7cb01e02013-08-29 16:05:02 -0700521config TPM
522 bool
523 default n
Vadim Bendebury26588702016-06-02 20:43:19 -0700524 select LPC_TPM if MAINBOARD_HAS_LPC_TPM
525 select I2C_TPM if !MAINBOARD_HAS_LPC_TPM && !SPI_TPM
Stefan Reinauer7cb01e02013-08-29 16:05:02 -0700526 help
527 Enable this option to enable TPM support in coreboot.
528
529 If unsure, say N.
530
Vadim Bendebury26588702016-06-02 20:43:19 -0700531config TPM2
532 bool
533 select LPC_TPM if MAINBOARD_HAS_LPC_TPM
534 select I2C_TPM if !MAINBOARD_HAS_LPC_TPM && !SPI_TPM
535 help
536 Enable this option to enable TPM2 support in coreboot.
537
538 If unsure, say N.
539
Patrick Georgi0588d192009-08-12 15:00:51 +0000540config HEAP_SIZE
541 hex
Myles Watson04000f42009-10-16 19:12:49 +0000542 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000543
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700544config STACK_SIZE
545 hex
Julius Werner66a476a2015-10-12 16:45:21 -0700546 default 0x1000 if ARCH_X86
547 default 0x0
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700548
Patrick Georgi0588d192009-08-12 15:00:51 +0000549config MAX_CPUS
550 int
551 default 1
552
Stefan Reinauera48ca842015-04-04 01:58:28 +0200553source "src/console/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +0000554
555config HAVE_ACPI_RESUME
556 bool
557 default n
558
Kyösti Mälkki9d6f3652016-06-28 07:38:46 +0300559config ACPI_HUGE_LOWMEM_BACKUP
560 bool
Kyösti Mälkki43e9c932016-11-10 11:50:21 +0200561 default n
Kyösti Mälkki9d6f3652016-06-28 07:38:46 +0300562 help
563 On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.
564
Aaron Durbin87c9fae2016-01-22 15:26:04 -0600565config RESUME_PATH_SAME_AS_BOOT
566 bool
567 default y if ARCH_X86
568 depends on HAVE_ACPI_RESUME
569 help
570 This option indicates that when a system resumes it takes the
571 same path as a regular boot. e.g. an x86 system runs from the
572 reset vector at 0xfffffff0 on both resume and warm/cold boot.
573
Patrick Georgi0588d192009-08-12 15:00:51 +0000574config HAVE_HARD_RESET
575 bool
Uwe Hermann748475b2009-10-09 11:47:21 +0000576 default n
Patrick Georgi37bdb872010-02-27 08:39:04 +0000577 help
578 This variable specifies whether a given board has a hard_reset
579 function, no matter if it's provided by board code or chipset code.
580
Timothy Pearson44d53422015-05-18 16:04:10 -0500581config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
582 bool
Kyösti Mälkkib5664de2016-07-08 13:33:00 +0300583 depends on EARLY_CBMEM_INIT
Timothy Pearson44d53422015-05-18 16:04:10 -0500584 default n
585
Timothy Pearson7b22d842015-08-28 19:52:05 -0500586config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
587 bool
Kyösti Mälkkib5664de2016-07-08 13:33:00 +0300588 depends on EARLY_CBMEM_INIT
Timothy Pearson7b22d842015-08-28 19:52:05 -0500589 default n
590 help
591 This should be enabled on certain plaforms, such as the AMD
592 SR565x, that cannot handle concurrent CBFS accesses from
593 multiple APs during early startup.
594
Timothy Pearsonc764c742015-08-28 20:48:17 -0500595config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
596 bool
Kyösti Mälkkib5664de2016-07-08 13:33:00 +0300597 depends on EARLY_CBMEM_INIT
Timothy Pearsonc764c742015-08-28 20:48:17 -0500598 default n
599
Aaron Durbina4217912013-04-29 22:31:51 -0500600config HAVE_MONOTONIC_TIMER
601 def_bool n
602 help
603 The board/chipset provides a monotonic timer.
604
Aaron Durbine5e36302014-09-25 10:05:15 -0500605config GENERIC_UDELAY
606 def_bool n
607 depends on HAVE_MONOTONIC_TIMER
608 help
609 The board/chipset uses a generic udelay function utilizing the
610 monotonic timer.
611
Aaron Durbin340ca912013-04-30 09:58:12 -0500612config TIMER_QUEUE
613 def_bool n
614 depends on HAVE_MONOTONIC_TIMER
615 help
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300616 Provide a timer queue for performing time-based callbacks.
Aaron Durbin340ca912013-04-30 09:58:12 -0500617
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500618config COOP_MULTITASKING
619 def_bool n
Aaron Durbin38c326d2013-05-06 12:22:23 -0500620 depends on TIMER_QUEUE && ARCH_X86
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500621 help
622 Cooperative multitasking allows callbacks to be multiplexed on the
623 main thread of ramstage. With this enabled it allows for multiple
624 execution paths to take place when they have udelay() calls within
625 their code.
626
627config NUM_THREADS
628 int
629 default 4
630 depends on COOP_MULTITASKING
631 help
632 How many execution threads to cooperatively multitask with.
633
Patrick Georgi0588d192009-08-12 15:00:51 +0000634config HAVE_OPTION_TABLE
635 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000636 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000637 help
638 This variable specifies whether a given board has a cmos.layout
639 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000640 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000641
Patrick Georgi0588d192009-08-12 15:00:51 +0000642config PIRQ_ROUTE
643 bool
644 default n
645
646config HAVE_SMI_HANDLER
647 bool
648 default n
649
650config PCI_IO_CFG_EXT
651 bool
652 default n
653
654config IOAPIC
655 bool
656 default n
657
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200658config CACHE_ROM_SIZE_OVERRIDE
Stefan Reinauer5b635792012-08-16 14:05:42 -0700659 hex
Martin Roth3b878122016-09-30 14:43:01 -0600660 default 0x0
Stefan Reinauer5b635792012-08-16 14:05:42 -0700661
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000662# TODO: Can probably be removed once all chipsets have kconfig options for it.
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000663config VIDEO_MB
664 int
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000665 default 0
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000666
Myles Watson45bb25f2009-09-22 18:49:08 +0000667config USE_WATCHDOG_ON_BOOT
668 bool
669 default n
670
671config VGA
672 bool
673 default n
674 help
675 Build board-specific VGA code.
676
677config GFXUMA
678 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000679 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000680 help
681 Enable Unified Memory Architecture for graphics.
682
Myles Watsonb8e20272009-10-15 13:35:47 +0000683config HAVE_ACPI_TABLES
684 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000685 help
686 This variable specifies whether a given board has ACPI table support.
687 It is usually set in mainboard/*/Kconfig.
Myles Watsonb8e20272009-10-15 13:35:47 +0000688
689config HAVE_MP_TABLE
690 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000691 help
692 This variable specifies whether a given board has MP table support.
693 It is usually set in mainboard/*/Kconfig.
694 Whether or not the MP table is actually generated by coreboot
695 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000696
697config HAVE_PIRQ_TABLE
698 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000699 help
700 This variable specifies whether a given board has PIRQ table support.
701 It is usually set in mainboard/*/Kconfig.
702 Whether or not the PIRQ table is actually generated by coreboot
703 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000704
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -0500705config MAX_PIRQ_LINKS
706 int
707 default 4
708 help
709 This variable specifies the number of PIRQ interrupt links which are
710 routable. On most chipsets, this is 4, INTA through INTD. Some
711 chipsets offer more than four links, commonly up to INTH. They may
712 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
713 table specifies links greater than 4, pirq_route_irqs will not
714 function properly, unless this variable is correctly set.
715
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200716config COMMON_FADT
717 bool
718 default n
719
Aaron Durbin9420a522015-11-17 16:31:00 -0600720config ACPI_NHLT
721 bool
722 default n
723 help
724 Build support for NHLT (non HD Audio) ACPI table generation.
725
Myles Watsond73c1b52009-10-26 15:14:07 +0000726#These Options are here to avoid "undefined" warnings.
727#The actual selection and help texts are in the following menu.
728
Uwe Hermann168b11b2009-10-07 16:15:40 +0000729menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000730
Myles Watsonb8e20272009-10-15 13:35:47 +0000731config GENERATE_MP_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800732 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
733 bool
734 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000735 help
736 Generate an MP table (conforming to the Intel MultiProcessor
737 specification 1.4) for this board.
738
739 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000740
Myles Watsonb8e20272009-10-15 13:35:47 +0000741config GENERATE_PIRQ_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800742 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
743 bool
744 default HAVE_PIRQ_TABLE
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000745 help
746 Generate a PIRQ table for this board.
747
748 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000749
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200750config GENERATE_SMBIOS_TABLES
751 depends on ARCH_X86
752 bool "Generate SMBIOS tables"
753 default y
754 help
755 Generate SMBIOS tables for this board.
756
757 If unsure, say Y.
758
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200759config SMBIOS_PROVIDED_BY_MOBO
760 bool
761 default n
762
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200763config MAINBOARD_SERIAL_NUMBER
764 string "SMBIOS Serial Number"
765 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200766 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200767 default "123456789"
Martin Roth595e7772015-04-26 18:53:26 -0600768 help
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200769 The Serial Number to store in SMBIOS structures.
770
771config MAINBOARD_VERSION
772 string "SMBIOS Version Number"
773 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200774 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200775 default "1.0"
776 help
777 The Version Number to store in SMBIOS structures.
778
779config MAINBOARD_SMBIOS_MANUFACTURER
780 string "SMBIOS Manufacturer"
781 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200782 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200783 default MAINBOARD_VENDOR
784 help
785 Override the default Manufacturer stored in SMBIOS structures.
786
787config MAINBOARD_SMBIOS_PRODUCT_NAME
788 string "SMBIOS Product name"
789 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200790 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200791 default MAINBOARD_PART_NUMBER
792 help
793 Override the default Product name stored in SMBIOS structures.
794
Myles Watson45bb25f2009-09-22 18:49:08 +0000795endmenu
796
Martin Roth21c06502016-02-04 19:52:27 -0700797source "payloads/Kconfig"
Peter Stugea758ca22009-09-17 16:21:31 +0000798
Uwe Hermann168b11b2009-10-07 16:15:40 +0000799menu "Debugging"
800
801# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000802config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000803 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200804 default n
Denis 'GNUtoo' Carikli3747ba12015-12-10 22:04:56 +0100805 depends on CONSOLE_SERIAL
Patrick Georgi0588d192009-08-12 15:00:51 +0000806 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000807 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000808 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000809
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200810config GDB_WAIT
811 bool "Wait for a GDB connection"
812 default n
813 depends on GDB_STUB
814 help
815 If enabled, coreboot will wait for a GDB connection.
816
Julius Wernerd82e0cf2015-02-17 17:27:23 -0800817config FATAL_ASSERTS
818 bool "Halt when hitting a BUG() or assertion error"
819 default n
820 help
821 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
822
Stefan Reinauerfe422182012-05-02 16:33:18 -0700823config DEBUG_CBFS
824 bool "Output verbose CBFS debug messages"
825 default n
Stefan Reinauerfe422182012-05-02 16:33:18 -0700826 help
827 This option enables additional CBFS related debug messages.
828
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000829config HAVE_DEBUG_RAM_SETUP
830 def_bool n
831
Uwe Hermann01ce6012010-03-05 10:03:50 +0000832config DEBUG_RAM_SETUP
833 bool "Output verbose RAM init debug messages"
834 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000835 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000836 help
837 This option enables additional RAM init related debug messages.
838 It is recommended to enable this when debugging issues on your
839 board which might be RAM init related.
840
841 Note: This option will increase the size of the coreboot image.
842
843 If unsure, say N.
844
Patrick Georgie82618d2010-10-01 14:50:12 +0000845config HAVE_DEBUG_CAR
846 def_bool n
847
Peter Stuge5015f792010-11-10 02:00:32 +0000848config DEBUG_CAR
849 def_bool n
850 depends on HAVE_DEBUG_CAR
851
852if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermanna953f372010-11-10 00:14:32 +0000853# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
854# printk(BIOS_DEBUG, ...) calls.
Patrick Georgie82618d2010-10-01 14:50:12 +0000855config DEBUG_CAR
856 bool "Output verbose Cache-as-RAM debug messages"
857 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000858 depends on HAVE_DEBUG_CAR
Patrick Georgie82618d2010-10-01 14:50:12 +0000859 help
860 This option enables additional CAR related debug messages.
Peter Stuge5015f792010-11-10 02:00:32 +0000861endif
Patrick Georgie82618d2010-10-01 14:50:12 +0000862
Myles Watson80e914ff2010-06-01 19:25:31 +0000863config DEBUG_PIRQ
864 bool "Check PIRQ table consistency"
865 default n
866 depends on GENERATE_PIRQ_TABLE
867 help
868 If unsure, say N.
869
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000870config HAVE_DEBUG_SMBUS
871 def_bool n
872
Uwe Hermann01ce6012010-03-05 10:03:50 +0000873config DEBUG_SMBUS
874 bool "Output verbose SMBus debug messages"
875 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000876 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000877 help
878 This option enables additional SMBus (and SPD) debug messages.
879
880 Note: This option will increase the size of the coreboot image.
881
882 If unsure, say N.
883
884config DEBUG_SMI
885 bool "Output verbose SMI debug messages"
886 default n
887 depends on HAVE_SMI_HANDLER
Martin Roth3a543182015-09-28 15:27:24 -0600888 select SPI_FLASH_SMM if SPI_CONSOLE
Uwe Hermann01ce6012010-03-05 10:03:50 +0000889 help
890 This option enables additional SMI related debug messages.
891
892 Note: This option will increase the size of the coreboot image.
893
894 If unsure, say N.
895
Stefan Reinauerbc0f7a62010-08-01 15:41:14 +0000896config DEBUG_SMM_RELOCATION
897 bool "Debug SMM relocation code"
898 default n
899 depends on HAVE_SMI_HANDLER
900 help
901 This option enables additional SMM handler relocation related
902 debug messages.
903
904 Note: This option will increase the size of the coreboot image.
905
906 If unsure, say N.
907
Uwe Hermanna953f372010-11-10 00:14:32 +0000908# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
909# printk(BIOS_DEBUG, ...) calls.
910config DEBUG_MALLOC
Stefan Reinauer95a63962012-11-13 17:00:01 -0800911 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
912 bool
Uwe Hermanna953f372010-11-10 00:14:32 +0000913 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000914 help
915 This option enables additional malloc related debug messages.
916
917 Note: This option will increase the size of the coreboot image.
918
919 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300920
921# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
922# printk(BIOS_DEBUG, ...) calls.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300923config DEBUG_ACPI
Stefan Reinauer95a63962012-11-13 17:00:01 -0800924 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
925 bool
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300926 default n
927 help
928 This option enables additional ACPI related debug messages.
929
930 Note: This option will slightly increase the size of the coreboot image.
931
932 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300933
Uwe Hermanna953f372010-11-10 00:14:32 +0000934# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
935# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000936config REALMODE_DEBUG
Stefan Reinauer95a63962012-11-13 17:00:01 -0800937 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
938 bool
Myles Watson6c9bc012010-09-07 22:30:15 +0000939 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000940 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000941 help
942 This option enables additional x86emu related debug messages.
943
944 Note: This option will increase the time to emulate a ROM.
945
946 If unsure, say N.
947
Uwe Hermann01ce6012010-03-05 10:03:50 +0000948config X86EMU_DEBUG
949 bool "Output verbose x86emu debug messages"
950 default n
951 depends on PCI_OPTION_ROM_RUN_YABEL
952 help
953 This option enables additional x86emu related debug messages.
954
955 Note: This option will increase the size of the coreboot image.
956
957 If unsure, say N.
958
959config X86EMU_DEBUG_JMP
960 bool "Trace JMP/RETF"
961 default n
962 depends on X86EMU_DEBUG
963 help
964 Print information about JMP and RETF opcodes from x86emu.
965
966 Note: This option will increase the size of the coreboot image.
967
968 If unsure, say N.
969
970config X86EMU_DEBUG_TRACE
971 bool "Trace all opcodes"
972 default n
973 depends on X86EMU_DEBUG
974 help
975 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000976
Uwe Hermann01ce6012010-03-05 10:03:50 +0000977 WARNING: This will produce a LOT of output and take a long time.
978
979 Note: This option will increase the size of the coreboot image.
980
981 If unsure, say N.
982
983config X86EMU_DEBUG_PNP
984 bool "Log Plug&Play accesses"
985 default n
986 depends on X86EMU_DEBUG
987 help
988 Print Plug And Play accesses made by option ROMs.
989
990 Note: This option will increase the size of the coreboot image.
991
992 If unsure, say N.
993
994config X86EMU_DEBUG_DISK
995 bool "Log Disk I/O"
996 default n
997 depends on X86EMU_DEBUG
998 help
999 Print Disk I/O related messages.
1000
1001 Note: This option will increase the size of the coreboot image.
1002
1003 If unsure, say N.
1004
1005config X86EMU_DEBUG_PMM
1006 bool "Log PMM"
1007 default n
1008 depends on X86EMU_DEBUG
1009 help
1010 Print messages related to POST Memory Manager (PMM).
1011
1012 Note: This option will increase the size of the coreboot image.
1013
1014 If unsure, say N.
1015
1016
1017config X86EMU_DEBUG_VBE
1018 bool "Debug VESA BIOS Extensions"
1019 default n
1020 depends on X86EMU_DEBUG
1021 help
1022 Print messages related to VESA BIOS Extension (VBE) functions.
1023
1024 Note: This option will increase the size of the coreboot image.
1025
1026 If unsure, say N.
1027
1028config X86EMU_DEBUG_INT10
1029 bool "Redirect INT10 output to console"
1030 default n
1031 depends on X86EMU_DEBUG
1032 help
1033 Let INT10 (i.e. character output) calls print messages to debug output.
1034
1035 Note: This option will increase the size of the coreboot image.
1036
1037 If unsure, say N.
1038
1039config X86EMU_DEBUG_INTERRUPTS
1040 bool "Log intXX calls"
1041 default n
1042 depends on X86EMU_DEBUG
1043 help
1044 Print messages related to interrupt handling.
1045
1046 Note: This option will increase the size of the coreboot image.
1047
1048 If unsure, say N.
1049
1050config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1051 bool "Log special memory accesses"
1052 default n
1053 depends on X86EMU_DEBUG
1054 help
1055 Print messages related to accesses to certain areas of the virtual
1056 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1057
1058 Note: This option will increase the size of the coreboot image.
1059
1060 If unsure, say N.
1061
1062config X86EMU_DEBUG_MEM
1063 bool "Log all memory accesses"
1064 default n
1065 depends on X86EMU_DEBUG
1066 help
1067 Print memory accesses made by option ROM.
1068 Note: This also includes accesses to fetch instructions.
1069
1070 Note: This option will increase the size of the coreboot image.
1071
1072 If unsure, say N.
1073
1074config X86EMU_DEBUG_IO
1075 bool "Log IO accesses"
1076 default n
1077 depends on X86EMU_DEBUG
1078 help
1079 Print I/O accesses made by option ROM.
1080
1081 Note: This option will increase the size of the coreboot image.
1082
1083 If unsure, say N.
1084
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +02001085config X86EMU_DEBUG_TIMINGS
1086 bool "Output timing information"
1087 default n
1088 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1089 help
1090 Print timing information needed by i915tool.
1091
1092 If unsure, say N.
1093
Stefan Reinauerdfb098d2011-11-17 12:50:54 -08001094config DEBUG_TPM
1095 bool "Output verbose TPM debug messages"
1096 default n
Vadim Bendebury26588702016-06-02 20:43:19 -07001097 depends on TPM || TPM2
Stefan Reinauerdfb098d2011-11-17 12:50:54 -08001098 help
1099 This option enables additional TPM related debug messages.
1100
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -07001101config DEBUG_SPI_FLASH
1102 bool "Output verbose SPI flash debug messages"
1103 default n
1104 depends on SPI_FLASH
1105 help
1106 This option enables additional SPI flash related debug messages.
1107
Kyösti Mälkki3be80cc2013-06-06 10:46:37 +03001108config DEBUG_USBDEBUG
1109 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1110 default n
1111 depends on USBDEBUG
1112 help
1113 This option enables additional USB 2.0 debug dongle related messages.
1114
1115 Select this to debug the connection of usbdebug dongle. Note that
1116 you need some other working console to receive the messages.
1117
Stefan Reinauer8e073822012-04-04 00:07:22 +02001118if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1119# Only visible with the right southbridge and loglevel.
1120config DEBUG_INTEL_ME
1121 bool "Verbose logging for Intel Management Engine"
1122 default n
1123 help
1124 Enable verbose logging for Intel Management Engine driver that
1125 is present on Intel 6-series chipsets.
1126endif
1127
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001128config TRACE
1129 bool "Trace function calls"
1130 default n
1131 help
1132 If enabled, every function will print information to console once
1133 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1134 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
Ben Gardner8420ad42015-11-18 10:46:53 -06001135 of calling function. Please note some printk related functions
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001136 are omitted from trace to have good looking console dumps.
Stefan Reinauerd37ab452012-12-18 16:23:28 -08001137
1138config DEBUG_COVERAGE
1139 bool "Debug code coverage"
1140 default n
1141 depends on COVERAGE
1142 help
1143 If enabled, the code coverage hooks in coreboot will output some
1144 information about the coverage data that is dumped.
1145
Jonathan Neuschäferfc04f9b2016-06-29 21:59:32 +02001146config DEBUG_BOOT_STATE
1147 bool "Debug boot state machine"
1148 default n
1149 help
1150 Control debugging of the boot state machine. When selected displays
1151 the state boundaries in ramstage.
1152
Jonathan Neuschäfer538e4462016-08-22 19:37:15 +02001153config DEBUG_PRINT_PAGE_TABLES
1154 bool "Print the page tables after construction"
1155 default n
1156 depends on ARCH_RISCV
1157 help
1158 After the page tables have been built, print them on the debug
1159 console.
1160
Nico Hubere84e62542016-10-05 17:43:56 +02001161config DEBUG_ADA_CODE
1162 bool "Compile debug code in Ada sources"
1163 default n
1164 help
1165 Add the compiler switch `-gnata` to compile code guarded by
1166 `pragma Debug`.
1167
Uwe Hermann168b11b2009-10-07 16:15:40 +00001168endmenu
1169
Myles Watsond73c1b52009-10-26 15:14:07 +00001170# These probably belong somewhere else, but they are needed somewhere.
Myles Watsond73c1b52009-10-26 15:14:07 +00001171config ENABLE_APIC_EXT_ID
1172 bool
1173 default n
Myles Watson2e672732009-11-12 16:38:03 +00001174
1175config WARNINGS_ARE_ERRORS
1176 bool
Edward O'Callaghan63f6dc72014-11-18 03:17:54 +11001177 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +00001178
Peter Stuge51eafde2010-10-13 06:23:02 +00001179# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1180# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1181# mutually exclusive. One of these options must be selected in the
1182# mainboard Kconfig if the chipset supports enabling and disabling of
1183# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1184# in mainboard/Kconfig to know if the button should be enabled or not.
1185
1186config POWER_BUTTON_DEFAULT_ENABLE
1187 def_bool n
1188 help
1189 Select when the board has a power button which can optionally be
1190 disabled by the user.
1191
1192config POWER_BUTTON_DEFAULT_DISABLE
1193 def_bool n
1194 help
1195 Select when the board has a power button which can optionally be
1196 enabled by the user, e.g. when the board ships with a jumper over
1197 the power switch contacts.
1198
1199config POWER_BUTTON_FORCE_ENABLE
1200 def_bool n
1201 help
1202 Select when the board requires that the power button is always
1203 enabled.
1204
1205config POWER_BUTTON_FORCE_DISABLE
1206 def_bool n
1207 help
1208 Select when the board requires that the power button is always
1209 disabled, e.g. when it has been hardwired to ground.
1210
1211config POWER_BUTTON_IS_OPTIONAL
1212 bool
1213 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1214 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1215 help
1216 Internal option that controls ENABLE_POWER_BUTTON visibility.
Duncan Laurie72748002013-10-31 08:26:23 -07001217
1218config REG_SCRIPT
1219 bool
Duncan Laurie72748002013-10-31 08:26:23 -07001220 default n
1221 help
1222 Internal option that controls whether we compile in register scripts.
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001223
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001224config MAX_REBOOT_CNT
1225 int
1226 default 3
Timothy Pearson17ada2e2015-03-18 01:31:34 -05001227 help
1228 Internal option that sets the maximum number of bootblock executions allowed
1229 with the normal image enabled before assuming the normal image is defective
Vadim Bendebury9c9c3362014-07-23 09:40:02 -07001230 and switching to the fallback image.
Martin Roth59ff3402016-02-09 09:06:46 -07001231
1232config CBFS_SIZE
1233 hex
1234 default ROM_SIZE
1235 help
1236 This is the part of the ROM actually managed by CBFS. Set it to be
Elyes HAOUAS45de1fe2016-07-29 07:31:54 +02001237 equal to the full ROM size if that hasn't been overridden by the
Martin Roth59ff3402016-02-09 09:06:46 -07001238 chipset or mainboard.
Lee Leahy10605352016-02-14 17:01:40 -08001239
Lee Leahyfc3741f2016-05-26 17:12:17 -07001240config CREATE_BOARD_CHECKLIST
1241 bool
1242 default n
1243 help
1244 When selected, creates a webpage showing the implementation status for
1245 the board. Routines highlighted in green are complete, yellow are
1246 optional and red are required and must be implemented. A table is
1247 produced for each stage of the boot process except the bootblock. The
1248 red items may be used as an implementation checklist for the board.
1249
1250config MAKE_CHECKLIST_PUBLIC
1251 bool
1252 default n
1253 help
1254 When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
1255 is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
1256 directory.
1257
1258config CHECKLIST_DATA_FILE_LOCATION
1259 string
1260 help
1261 Location of the <stage>_complete.dat and <stage>_optional.dat files
1262 that are consumed during checklist processing. <stage>_complete.dat
1263 contains the symbols that are expected to be in the resulting image.
1264 <stage>_optional.dat is a subset of <stage>_complete.dat and contains
1265 a list of weak symbols which the resulting image may consume. Other
1266 symbols contained only in <stage>_complete.dat will be flagged as
1267 required and not implemented if a weak implementation is found in the
1268 resulting image.
Nico Hubere0ed9022016-10-07 12:58:17 +02001269
1270config RAMSTAGE_ADA
1271 def_bool n
1272 help
1273 Selected by features that use Ada code in ramstage.
Nico Huberc83239e2016-10-05 17:46:49 +02001274
1275config RAMSTAGE_LIBHWBASE
1276 def_bool n
1277 select RAMSTAGE_ADA
1278 help
1279 Selected by features that require `libhwbase` in ramstage.
1280
1281config HWBASE_DYNAMIC_MMIO
1282 def_bool y