| Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 18 | * Foundation, Inc. |
| Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
| Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 21 | /* VGA stuff */ |
| Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 22 | #define SR_INDEX 0x3c4 |
| 23 | #define SR_DATA 0x3c5 |
| 24 | #define CRTM_INDEX 0x3b4 |
| 25 | #define CRTM_DATA 0x3b5 |
| 26 | #define CRTC_INDEX 0x3d4 |
| 27 | #define CRTC_DATA 0x3d5 |
| Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 28 | |
| Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 29 | /* Memory controller registers */ |
| Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 30 | #define RANK0_END 0x40 |
| 31 | #define RANK1_END 0x41 |
| 32 | #define RANK2_END 0x42 |
| 33 | #define RANK3_END 0x43 |
| 34 | #define RANK0_START 0x48 |
| 35 | #define RANK1_START 0x49 |
| 36 | #define RANK2_START 0x4a |
| 37 | #define RANK3_START 0x4b |
| 38 | #define DDR_PAGE_CTL 0x69 |
| 39 | #define DRAM_REFRESH_COUNTER 0x6a |
| 40 | #define DRAM_MISC_CTL 0x6b |
| 41 | #define CH_A_DQS_OUTPUT_DELAY 0x70 |
| 42 | #define CH_A_MD_OUTPUT_DELAY 0x71 |
| 43 | |
| Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 44 | /* RAM init commands */ |
| Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 45 | #define RAM_COMMAND_NORMAL 0x0 |
| 46 | #define RAM_COMMAND_NOP 0x1 |
| 47 | #define RAM_COMMAND_PRECHARGE 0x2 |
| 48 | #define RAM_COMMAND_MRS 0x3 |
| 49 | #define RAM_COMMAND_CBR 0x4 |