Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include <arch/romcc_io.h> |
| 23 | #include <northbridge/intel/sandybridge/pcie_config.c> |
| 24 | #include "pch.h" |
| 25 | |
| 26 | void intel_pch_finalize_smm(void) |
| 27 | { |
| 28 | /* Set SPI opcode menu */ |
| 29 | RCBA16(0x3894) = SPI_OPPREFIX; |
| 30 | RCBA16(0x3896) = SPI_OPTYPE; |
| 31 | RCBA32(0x3898) = SPI_OPMENU_LOWER; |
| 32 | RCBA32(0x389c) = SPI_OPMENU_UPPER; |
| 33 | |
| 34 | /* Lock SPIBAR */ |
| 35 | RCBA32_OR(0x3804, (1 << 15)); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 36 | |
| 37 | /* TCLOCKDN: TC Lockdown */ |
| 38 | RCBA32_OR(0x0050, (1 << 31)); |
| 39 | |
| 40 | /* BIOS Interface Lockdown */ |
| 41 | RCBA32_OR(0x3410, (1 << 0)); |
| 42 | |
| 43 | /* Function Disable SUS Well Lockdown */ |
| 44 | RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); |
| 45 | |
| 46 | /* Global SMI Lock */ |
| 47 | pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); |
| 48 | |
| 49 | /* GEN_PMCON Lock */ |
| 50 | pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); |
| 51 | |
| 52 | /* R/WO registers */ |
| 53 | RCBA32(0x21a4) = RCBA32(0x21a4); |
| 54 | pcie_write_config32(PCI_DEV(0, 27, 0), 0x74, |
| 55 | pcie_read_config32(PCI_DEV(0, 27, 0), 0x74)); |
| 56 | } |