Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 2 | |
Angel Pons | 24f4623 | 2021-04-17 12:08:15 +0200 | [diff] [blame] | 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 5 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 7 | #include <device/device.h> |
| 8 | #include <device/pci.h> |
| 9 | #include <device/pci_def.h> |
Subrata Banik | 211be9c | 2022-04-13 12:13:09 +0530 | [diff] [blame] | 10 | #include <intelblocks/gpmr.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 11 | #include <intelblocks/pcr.h> |
Michael Niewöhner | 2bd2be5 | 2020-03-03 20:47:01 +0100 | [diff] [blame] | 12 | #include <intelblocks/pmclib.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 13 | #include <intelblocks/tco.h> |
| 14 | #include <soc/iomap.h> |
| 15 | #include <soc/pci_devs.h> |
| 16 | #include <soc/pcr_ids.h> |
| 17 | #include <soc/pm.h> |
| 18 | #include <soc/smbus.h> |
| 19 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 20 | /* SMBUS TCO base address. */ |
| 21 | #define TCOBASE 0x50 |
| 22 | #define TCOCTL 0x54 |
| 23 | #define TCO_BASE_EN (1 << 8) |
Michael Niewöhner | 3c20cba | 2019-09-22 13:27:20 +0200 | [diff] [blame] | 24 | #define TCO_BASE_LOCK (1 << 0) |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 25 | |
| 26 | /* Get base address of TCO I/O registers. */ |
| 27 | static uint16_t tco_get_bar(void) |
| 28 | { |
| 29 | return TCO_BASE_ADDRESS; |
| 30 | } |
| 31 | |
| 32 | uint16_t tco_read_reg(uint16_t tco_reg) |
| 33 | { |
| 34 | uint16_t tcobase; |
| 35 | |
| 36 | tcobase = tco_get_bar(); |
| 37 | |
| 38 | return inw(tcobase + tco_reg); |
| 39 | } |
| 40 | |
| 41 | void tco_write_reg(uint16_t tco_reg, uint16_t value) |
| 42 | { |
| 43 | uint16_t tcobase; |
| 44 | |
| 45 | tcobase = tco_get_bar(); |
| 46 | |
| 47 | outw(value, tcobase + tco_reg); |
| 48 | } |
| 49 | |
| 50 | void tco_lockdown(void) |
| 51 | { |
| 52 | uint16_t tcocnt; |
Michael Niewöhner | 3c20cba | 2019-09-22 13:27:20 +0200 | [diff] [blame] | 53 | const pci_devfn_t dev = PCH_DEV_SMBUS; |
| 54 | |
| 55 | /* TCO base address lockdown */ |
| 56 | pci_or_config32(dev, TCOCTL, TCO_BASE_LOCK); |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 57 | |
| 58 | /* TCO Lock down */ |
| 59 | tcocnt = tco_read_reg(TCO1_CNT); |
| 60 | tcocnt |= TCO_LOCK; |
| 61 | tco_write_reg(TCO1_CNT, tcocnt); |
| 62 | } |
| 63 | |
| 64 | uint32_t tco_reset_status(void) |
| 65 | { |
| 66 | uint16_t tco1_sts; |
| 67 | uint16_t tco2_sts; |
| 68 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 69 | /* TCO Status 1 register */ |
| 70 | tco1_sts = tco_read_reg(TCO1_STS); |
Michael Niewöhner | 04b0206 | 2020-03-03 18:33:00 +0100 | [diff] [blame] | 71 | tco_write_reg(TCO1_STS, tco1_sts); |
| 72 | |
| 73 | /* TCO Status 2 register */ |
| 74 | tco2_sts = tco_read_reg(TCO2_STS); |
| 75 | tco_write_reg(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO); |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 76 | |
| 77 | return (tco2_sts << 16) | tco1_sts; |
| 78 | } |
| 79 | |
| 80 | /* Stop TCO timer */ |
| 81 | static void tco_timer_disable(void) |
| 82 | { |
| 83 | uint16_t tcocnt; |
| 84 | |
| 85 | /* Program TCO timer halt */ |
| 86 | tcocnt = tco_read_reg(TCO1_CNT); |
| 87 | tcocnt |= TCO_TMR_HLT; |
| 88 | tco_write_reg(TCO1_CNT, tcocnt); |
| 89 | } |
| 90 | |
Michael Niewöhner | 2bd2be5 | 2020-03-03 20:47:01 +0100 | [diff] [blame] | 91 | /* Enable and initialize TCO intruder SMI */ |
| 92 | static void tco_intruder_smi_enable(void) |
| 93 | { |
| 94 | uint16_t tcocnt; |
| 95 | |
| 96 | /* Make TCO issue an SMI on INTRD_DET assertion */ |
| 97 | tcocnt = tco_read_reg(TCO2_CNT); |
| 98 | tcocnt &= ~TCO_INTRD_SEL_MASK; |
| 99 | tcocnt |= TCO_INTRD_SEL_SMI; |
| 100 | tco_write_reg(TCO2_CNT, tcocnt); |
| 101 | } |
| 102 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 103 | /* Enable TCO BAR using SMBUS TCO base to access TCO related register */ |
| 104 | static void tco_enable_bar(void) |
| 105 | { |
| 106 | uint32_t reg32; |
| 107 | uint16_t tcobase; |
Angel Pons | 24f4623 | 2021-04-17 12:08:15 +0200 | [diff] [blame] | 108 | const pci_devfn_t dev = PCH_DEV_SMBUS; |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 109 | |
| 110 | /* Disable TCO in SMBUS Device first before changing Base Address */ |
| 111 | reg32 = pci_read_config32(dev, TCOCTL); |
| 112 | reg32 &= ~TCO_BASE_EN; |
| 113 | pci_write_config32(dev, TCOCTL, reg32); |
| 114 | |
| 115 | /* Program TCO Base */ |
| 116 | tcobase = tco_get_bar(); |
| 117 | pci_write_config32(dev, TCOBASE, tcobase); |
| 118 | |
| 119 | /* Enable TCO in SMBUS */ |
| 120 | pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_EN); |
| 121 | |
Subrata Banik | 211be9c | 2022-04-13 12:13:09 +0530 | [diff] [blame] | 122 | /* Program TCO Base Address */ |
| 123 | gpmr_write32(GPMR_TCOBASE, tcobase | GPMR_TCOEN); |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | /* |
| 127 | * Enable TCO BAR using SMBUS TCO base to access TCO related register |
| 128 | * also disable the timer. |
| 129 | */ |
| 130 | void tco_configure(void) |
| 131 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 132 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS)) |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 133 | tco_enable_bar(); |
| 134 | |
| 135 | tco_timer_disable(); |
Michael Niewöhner | 2bd2be5 | 2020-03-03 20:47:01 +0100 | [diff] [blame] | 136 | |
| 137 | /* Enable intruder interrupt if TCO interrupts are enabled*/ |
| 138 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)) |
| 139 | tco_intruder_smi_enable(); |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 140 | } |