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Angel Pons6ad91762020-04-03 01:23:24 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Mario Scheithauer092db952017-01-31 15:45:13 +01002
Ravi Sarawadiefa606b2017-08-04 16:26:09 -07003#include <console/console.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +02004#include <device/mmio.h>
Mario Scheithauer092db952017-01-31 15:45:13 +01005#include <device/device.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02006#include <device/pci_ops.h>
Mario Scheithauerb83858a2017-09-05 15:32:49 +02007#include <device/pci_ids.h>
Mario Scheithauer480eab02017-02-16 13:39:16 +01008#include <hwilib.h>
9#include <i210.h>
Mario Scheithauer0af272c2018-04-10 12:40:11 +020010#include <intelblocks/cpulib.h>
Mario Scheithauer0af272c2018-04-10 12:40:11 +020011#include <intelblocks/systemagent.h>
Ravi Sarawadiefa606b2017-08-04 16:26:09 -070012#include <soc/pci_devs.h>
13#include <string.h>
Werner Zehefd0eb32017-09-12 08:58:44 +020014#include <timer.h>
Mario Scheithauerd127be12018-04-23 10:55:39 +020015#include <baseboard/variants.h>
Elyes HAOUASe39db682019-05-15 21:12:31 +020016#include <types.h>
Mario Scheithauer480eab02017-02-16 13:39:16 +010017
18#define MAX_PATH_DEPTH 12
19#define MAX_NUM_MAPPINGS 10
20
Mario Scheithauer0af272c2018-04-10 12:40:11 +020021#define BIOS_MAILBOX_WAIT_MAX_MS 1000
22#define BIOS_MAILBOX_DATA 0x7080
23#define BIOS_MAILBOX_INTERFACE 0x7084
24#define RUN_BUSY_STS (1 << 31)
25
Werner Zehd5de0632018-09-19 11:06:22 +020026/*
27 * SPI Opcode Menu setup for SPIBAR lock down
28 * should support most common flash chips.
29 */
30#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
31#define SPI_OPTYPE_0 0x01 /* Write, no address */
32
33#define SPI_OPMENU_1 0x02 /* PP: Page Program */
34#define SPI_OPTYPE_1 0x03 /* Write, address required */
35
36#define SPI_OPMENU_2 0x03 /* READ: Read Data */
37#define SPI_OPTYPE_2 0x02 /* Read, address required */
38
39#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
40#define SPI_OPTYPE_3 0x00 /* Read, no address */
41
42#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
43#define SPI_OPTYPE_4 0x03 /* Write, address required */
44
45#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
46#define SPI_OPTYPE_5 0x00 /* Read, no address */
47
48#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
49#define SPI_OPTYPE_6 0x03 /* Write, address required */
50
51#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
52#define SPI_OPTYPE_7 0x02 /* Read, address required */
53
54#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
55 (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
56#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
57 (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
58
59#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
60 (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
61 (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
62 (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
63
64#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
65
66#define SPIBAR_OFFSET 0x3800
67#define SPI_REG_PREOP_OPTYPE 0xa4
68#define SPI_REG_OPMENU_L 0xa8
69#define SPI_REG_OPMENU_H 0xac
70
Mario Scheithauer7815c072019-07-17 09:40:33 +020071#define SD_CAP_BYP 0x810
72#define SD_CAP_BYP_EN 0x5A
73#define SD_CAP_BYP_REG1 0x814
74
Mario Scheithauer480eab02017-02-16 13:39:16 +010075/** \brief This function can decide if a given MAC address is valid or not.
76 * Currently, addresses filled with 0xff or 0x00 are not valid.
77 * @param mac Buffer to the MAC address to check
78 * @return 0 if address is not valid, otherwise 1
79 */
80static uint8_t is_mac_adr_valid(uint8_t mac[6])
81{
82 uint8_t buf[6];
83
84 memset(buf, 0, sizeof(buf));
85 if (!memcmp(buf, mac, sizeof(buf)))
86 return 0;
87 memset(buf, 0xff, sizeof(buf));
88 if (!memcmp(buf, mac, sizeof(buf)))
89 return 0;
90 return 1;
91}
92
93/** \brief This function will search for a MAC address which can be assigned
94 * to a MACPHY.
95 * @param dev pointer to PCI device
96 * @param mac buffer where to store the MAC address
97 * @return cb_err CB_ERR or CB_SUCCESS
98 */
99enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6])
100{
101 struct bus *parent = dev->bus;
102 uint8_t buf[16], mapping[16], i = 0, chain_len = 0;
103
104 memset(buf, 0, sizeof(buf));
105 memset(mapping, 0, sizeof(mapping));
106
107 /* The first entry in the tree is the device itself. */
108 buf[0] = dev->path.pci.devfn;
109 chain_len = 1;
110 for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) {
111 buf[i] = parent->dev->path.pci.devfn;
112 chain_len++;
113 parent = parent->dev->bus;
114 }
115 if (i == MAX_PATH_DEPTH) {
116 /* The path is deeper than MAX_PATH_DEPTH devices, error. */
117 printk(BIOS_ERR, "Too many bridges for %s\n", dev_path(dev));
118 return CB_ERR;
119 }
120 /*
121 * Now construct the mapping based on the device chain starting from
122 * root bridge device to the device itself.
123 */
124 mapping[0] = 1;
125 mapping[1] = chain_len;
126 for (i = 0; i < chain_len; i++)
127 mapping[i + 4] = buf[chain_len - i - 1];
128
129 /* Open main hwinfo block */
130 if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
131 return CB_ERR;
132 /* Now try to find a valid MAC address in hwinfo for this mapping.*/
133 for (i = 0; i < MAX_NUM_MAPPINGS; i++) {
134 if ((hwilib_get_field(XMac1Mapping + i, buf, 16) == 16) &&
135 !(memcmp(buf, mapping, chain_len + 4))) {
136 /* There is a matching mapping available, get MAC address. */
137 if ((hwilib_get_field(XMac1 + i, mac, 6) == 6) &&
138 (is_mac_adr_valid(mac))) {
139 return CB_SUCCESS;
140 } else {
141 return CB_ERR;
142 }
143 } else
144 continue;
145 }
146 /* No MAC address found for */
147 return CB_ERR;
148}
Mario Scheithauer092db952017-01-31 15:45:13 +0100149
Mario Scheithauer0af272c2018-04-10 12:40:11 +0200150/** \brief This function fixes an accuracy issue with IDT PMIC.
151 * The current reported system power consumption is higher than the
152 * actual consumption. With a correction of slope and offset for Vcc
153 * and Vnn, the issue is solved.
154 */
155static void config_pmic_imon(void)
156{
157 struct stopwatch sw;
158 uint32_t power_max;
159
160 printk(BIOS_DEBUG, "PMIC: Configure PMIC IMON - Start\n");
161
162 /* Calculate CPU TDP in mW */
163 power_max = cpu_get_power_max();
164 printk(BIOS_INFO, "PMIC: CPU TDP %d mW.\n", power_max);
165
166 /*
167 * Fix Vnn slope and offset value.
168 * slope = 0x4a4 # 2.32
169 * offset = 0xfa0d # -2.975
170 */
171 stopwatch_init_msecs_expire(&sw, BIOS_MAILBOX_WAIT_MAX_MS);
172 /* Read P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR and check RUN_BUSY. */
173 while ((MCHBAR32(BIOS_MAILBOX_INTERFACE) & RUN_BUSY_STS)) {
174 if (stopwatch_expired(&sw)) {
175 printk(BIOS_ERR, "PMIC: Power consumption measurement "
176 "setup fails for Vnn.\n");
177 return;
178 }
179 }
180 /* Set Vnn values into P_CR_BIOS_MAILBOX_DATA_0_0_0_MCHBAR. */
181 MCHBAR32(BIOS_MAILBOX_DATA) = 0xfa0d04a4;
182 /* Set command, address and busy bit. */
183 MCHBAR32(BIOS_MAILBOX_INTERFACE) = 0x8000011d;
184 printk(BIOS_DEBUG, "PMIC: Fix Vnn slope and offset value.\n");
185
186 /*
187 * Fix Vcc slope and offset value.
188 * Premium and High SKU:
189 * slope = 0x466 # 2.2
190 * offset = 0xe833 # -11.9
191 * Low and Intermediate SKU:
192 * slope = 0x3b3 # 1.85
193 * offset = 0xed33 # -9.4
194 */
195 stopwatch_init_msecs_expire(&sw, BIOS_MAILBOX_WAIT_MAX_MS);
196 while ((MCHBAR32(BIOS_MAILBOX_INTERFACE) & RUN_BUSY_STS)) {
197 if (stopwatch_expired(&sw)) {
198 printk(BIOS_ERR, "PMIC: Power consumption measurement "
199 "setup fails for Vcc.\n");
200 return;
201 }
202 }
203
204 /*
205 * CPU TDP limit between Premium/High and Low/Intermediate SKU
206 * is 9010 mW.
207 */
208 if (power_max > 9010) {
209 MCHBAR32(BIOS_MAILBOX_DATA) = 0xe8330466;
210 MCHBAR32(BIOS_MAILBOX_INTERFACE) = 0x8000001d;
211 printk(BIOS_INFO, "PMIC: Fix Vcc for Premium SKU.\n");
212 } else {
213 MCHBAR32(BIOS_MAILBOX_DATA) = 0xed3303b3;
214 MCHBAR32(BIOS_MAILBOX_INTERFACE) = 0x8000001d;
215 printk(BIOS_INFO, "PMIC: Fix Vcc for Low SKU.\n");
216 }
217
218 printk(BIOS_DEBUG, "PMIC: Configure PMIC IMON - End\n");
219}
220
Mario Scheithauer092db952017-01-31 15:45:13 +0100221static void mainboard_init(void *chip_info)
222{
Mario Scheithauer2d981202017-03-27 13:25:57 +0200223 const struct pad_config *pads;
224 size_t num;
225
Mario Scheithauerd127be12018-04-23 10:55:39 +0200226 pads = variant_gpio_table(&num);
Mario Scheithauer2d981202017-03-27 13:25:57 +0200227 gpio_configure_pads(pads, num);
Mario Scheithauer0af272c2018-04-10 12:40:11 +0200228
229 config_pmic_imon();
Mario Scheithauer092db952017-01-31 15:45:13 +0100230}
231
Mario Scheithauer956a9f62017-03-29 17:09:37 +0200232static void mainboard_final(void *chip_info)
233{
Mario Scheithauerb83858a2017-09-05 15:32:49 +0200234 uint16_t cmd = 0;
Elyes HAOUAS47503cd2018-05-04 21:58:51 +0200235 struct device *dev = NULL;
Werner Zehd5de0632018-09-19 11:06:22 +0200236 void *spi_base = NULL;
Mario Scheithauer956a9f62017-03-29 17:09:37 +0200237
Mario Scheithauer61413532018-04-25 14:05:09 +0200238 /* Do board specific things */
239 variant_mainboard_final();
Mario Scheithauerb83858a2017-09-05 15:32:49 +0200240
241 /* Set Master Enable for on-board PCI device. */
242 dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0);
243 if (dev) {
244 cmd = pci_read_config16(dev, PCI_COMMAND);
245 cmd |= PCI_COMMAND_MASTER;
246 pci_write_config16(dev, PCI_COMMAND, cmd);
247 }
Werner Zehd5de0632018-09-19 11:06:22 +0200248 /* Set up SPI OPCODE menu before the controller is locked. */
249 dev = PCH_DEV_SPI;
250 spi_base = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
251 if (!spi_base)
252 return;
253 write32((spi_base + SPI_REG_PREOP_OPTYPE),
254 ((SPI_OPTYPE << 16) | SPI_OPPREFIX));
255 write32((spi_base + SPI_REG_OPMENU_L), SPI_OPMENU_LOWER);
256 write32((spi_base + SPI_REG_OPMENU_H), SPI_OPMENU_UPPER);
Mario Scheithauer7815c072019-07-17 09:40:33 +0200257
258 /* Set SD-Card speed to HS mode only. */
259 dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
260 if (dev) {
261 uint32_t reg;
262 struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
263 if (!res)
264 return;
265
266 write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN);
267 reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0));
268 /* Disable all UHS-I SD-Card speed modes, keep only HS mode. */
269 reg &= ~0x2000f800;
270 write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg);
271 }
Mario Scheithauer956a9f62017-03-29 17:09:37 +0200272}
273
Mario Scheithauer61413532018-04-25 14:05:09 +0200274/* The following function performs board specific things. */
275void __weak variant_mainboard_final(void)
Werner Zehefd0eb32017-09-12 08:58:44 +0200276{
Werner Zehefd0eb32017-09-12 08:58:44 +0200277}
278
Mario Scheithauer092db952017-01-31 15:45:13 +0100279struct chip_operations mainboard_ops = {
280 .init = mainboard_init,
Mario Scheithauer956a9f62017-03-29 17:09:37 +0200281 .final = mainboard_final,
Mario Scheithauer092db952017-01-31 15:45:13 +0100282};