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review.coreboot.org / coreboot / 2ae9cce87a9aee32b465a50d8ea3bb888c97eb68 / . / src / ec / google / chromeec / Kconfig
blob: 2e4affc975ef2d036c49efd0770cc5a0da860071 [file] [log] [blame]
Stefan Reinauerd6682e82013-02-21 15:39:35 -0800[diff] [blame]1config EC_GOOGLE_CHROMEEC
2 bool
3 help
4 Google's Chrome EC
5
Shawn Nematbakhsh37b7a662015-03-24 11:07:51 -0700[diff] [blame]6config EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
7 depends on EC_GOOGLE_CHROMEEC_LPC
8 def_bool n
9 help
10 When defined, ACPI accesses EC memmap data on ports 66h/62h. When
11 not defined, the memmap data is instead accessed on 900h-9ffh via
12 the LPC bus.
13
Hung-Te Lin6bfbb332013-04-15 18:27:24 +0800[diff] [blame]14config EC_GOOGLE_CHROMEEC_I2C
Gabe Black3fb30ee2013-07-09 13:15:05 -0700[diff] [blame]15 depends on EC_GOOGLE_CHROMEEC
Hung-Te Lina904f9e2013-04-11 15:58:12 +0800[diff] [blame]16 bool
Gabe Black3fb30ee2013-07-09 13:15:05 -0700[diff] [blame]17 default n
Hung-Te Lin6bfbb332013-04-15 18:27:24 +0800[diff] [blame]18 help
19 Google's Chrome EC via I2C bus.
20
21config EC_GOOGLE_CHROMEEC_I2C_BUS
22 depends on EC_GOOGLE_CHROMEEC_I2C
23 hex "I2C bus for Google's Chrome EC"
24
25config EC_GOOGLE_CHROMEEC_I2C_CHIP
26 depends on EC_GOOGLE_CHROMEEC_I2C
27 hex
28 default 0x1e
29
Aaron Durbinaee78f02014-08-06 14:38:52 -0500[diff] [blame]30config EC_GOOGLE_CHROMEEC_I2C_PROTO3
31 depends on EC_GOOGLE_CHROMEEC_I2C
32 bool
33 default n
34 help
35 Use only proto3 for i2c EC communication.
36
Hung-Te Lin6bfbb332013-04-15 18:27:24 +0800[diff] [blame]37config EC_GOOGLE_CHROMEEC_LPC
Shawn Nematbakhsh37b7a662015-03-24 11:07:51 -0700[diff] [blame]38 depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play.
Hung-Te Lin0ee70622013-06-26 19:42:12 +0800[diff] [blame]39 def_bool y
Hung-Te Lina904f9e2013-04-11 15:58:12 +0800[diff] [blame]40 help
41 Google Chrome EC via LPC bus.
Hung-Te Lin0ee70622013-06-26 19:42:12 +0800[diff] [blame]42
Shawn Nematbakhsh5725ea32015-04-01 16:52:37 -0700[diff] [blame]43config EC_GOOGLE_CHROMEEC_MEC
44 depends on EC_GOOGLE_CHROMEEC_LPC
45 def_bool n
46 help
47 Microchip EC variant for LPC register access.
48
Duncan Laurieab40b912015-09-04 10:14:18 -0700[diff] [blame]49config EC_GOOGLE_CHROMEEC_PD
50 depends on EC_GOOGLE_CHROMEEC
51 def_bool n
52 help
53 Indicates that Google's Chrome USB PD chip is present.
54
Hung-Te Lin0ee70622013-06-26 19:42:12 +0800[diff] [blame]55config EC_GOOGLE_CHROMEEC_SPI
56 depends on EC_GOOGLE_CHROMEEC
57 def_bool n
58 help
59 Google's Chrome EC via SPI bus.
60
61config EC_GOOGLE_CHROMEEC_SPI_BUS
62 depends on EC_GOOGLE_CHROMEEC_SPI
Vladimir Serbinenko42f42ff2016-03-04 09:31:14 +0100[diff] [blame]63 hex
Hung-Te Lin0ee70622013-06-26 19:42:12 +0800[diff] [blame]64
David Hendricks767d2452014-09-27 20:04:49 -0700[diff] [blame]65config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
66 depends on EC_GOOGLE_CHROMEEC_SPI
67 int
68 default 0
69 help
70 Force delay after asserting /CS to allow EC to wakeup.
71
Hung-Te Lin0ee70622013-06-26 19:42:12 +0800[diff] [blame]72config EC_GOOGLE_CHROMEEC_SPI_CHIP
73 depends on EC_GOOGLE_CHROMEEC_SPI
74 hex
75 default 0
Patrick Georgie995dad22016-02-01 15:26:26 +0100[diff] [blame]76
77config EC_EXTERNAL_FIRMWARE
78 depends on EC_GOOGLE_CHROMEEC
79 def_bool n
80 help
81 Disable building EC firmware if it's already built externally (and
82 added manually.)
83
84config EC_GOOGLE_CHROMEEC_BOARDNAME
85 depends on EC_GOOGLE_CHROMEEC && !EC_EXTERNAL_FIRMWARE
86 string "Chrome EC board name for EC"
87 default ""
88 help
89 The board name used in the Chrome EC code base to build
90 the EC firmware. If set, the coreboot build with also
91 build the EC firmware and add it to the image.
92
93config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
94 depends on EC_GOOGLE_CHROMEEC_PD && !EC_EXTERNAL_FIRMWARE
95 string "Chrome EC board name for PD"
96 default ""
97 help
98 The board name used in the Chrome EC code base to build
99 the PD firmware. If set, the coreboot build with also
100 build the EC firmware and add it to the image.