Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Chromium OS Authors |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
| 21 | #include <console/console.h> |
| 22 | #include <delay.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | |
| 27 | #include "chip.h" |
| 28 | #include "haswell.h" |
| 29 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 30 | /* some vga option roms are used for several chipsets but they only have one |
| 31 | * PCI ID in their header. If we encounter such an option rom, we need to do |
| 32 | * the mapping ourselfes |
| 33 | */ |
| 34 | |
| 35 | u32 map_oprom_vendev(u32 vendev) |
| 36 | { |
| 37 | u32 new_vendev=vendev; |
| 38 | |
| 39 | switch (vendev) { |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 40 | case 0x80860402: /* GT1 Desktop */ |
| 41 | case 0x80860406: /* GT1 Mobile */ |
| 42 | case 0x8086040a: /* GT1 Server */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 43 | case 0x80860a06: /* GT1 ULT */ |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 44 | |
| 45 | case 0x80860412: /* GT2 Desktop */ |
| 46 | case 0x80860416: /* GT2 Mobile */ |
| 47 | case 0x8086041a: /* GT2 Server */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 48 | case 0x80860a16: /* GT2 ULT */ |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 49 | |
| 50 | case 0x80860422: /* GT3 Desktop */ |
| 51 | case 0x80860426: /* GT3 Mobile */ |
| 52 | case 0x8086042a: /* GT3 Server */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 53 | case 0x80860a26: /* GT3 ULT */ |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 54 | |
| 55 | new_vendev=0x80860406; /* GT1 Mobile */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 56 | break; |
| 57 | } |
| 58 | |
| 59 | return new_vendev; |
| 60 | } |
| 61 | |
| 62 | static struct resource *gtt_res = NULL; |
| 63 | |
| 64 | static inline u32 gtt_read(u32 reg) |
| 65 | { |
| 66 | return read32(gtt_res->base + reg); |
| 67 | } |
| 68 | |
| 69 | static inline void gtt_write(u32 reg, u32 data) |
| 70 | { |
| 71 | write32(gtt_res->base + reg, data); |
| 72 | } |
| 73 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 74 | #define GTT_RETRY 1000 |
| 75 | static int gtt_poll(u32 reg, u32 mask, u32 value) |
| 76 | { |
| 77 | unsigned try = GTT_RETRY; |
| 78 | u32 data; |
| 79 | |
| 80 | while (try--) { |
| 81 | data = gtt_read(reg); |
| 82 | if ((data & mask) == value) |
| 83 | return 1; |
| 84 | udelay(10); |
| 85 | } |
| 86 | |
| 87 | printk(BIOS_ERR, "GT init timeout\n"); |
| 88 | return 0; |
| 89 | } |
| 90 | |
| 91 | static void gma_pm_init_pre_vbios(struct device *dev) |
| 92 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 93 | printk(BIOS_DEBUG, "GT Power Management Init\n"); |
| 94 | |
| 95 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 96 | if (!gtt_res || !gtt_res->base) |
| 97 | return; |
| 98 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 99 | /* |
| 100 | * Enable RC6 |
| 101 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 102 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 103 | /* Enable Force Wake */ |
| 104 | gtt_write(0x0a180, 1 << 5); |
| 105 | gtt_write(0x0a188, 0x00010001); |
| 106 | gtt_poll(0x130044, 1 << 0, 1 << 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 107 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 108 | /* Enable counters and lock */ |
| 109 | gtt_write(0x0a248, 0x80000016); |
| 110 | gtt_write(0x0a000, 0x00070020); |
| 111 | gtt_write(0x0a180, 0xc5000020); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 112 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 113 | /* Enable DOP clock gating */ |
| 114 | gtt_write(0x09424, 0x00000001); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 115 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 116 | /* Enable unit level clock gating */ |
| 117 | gtt_write(0x09400, 0x00000080); |
| 118 | gtt_write(0x09404, 0x40401000); |
| 119 | gtt_write(0x09408, 0x00000000); |
| 120 | gtt_write(0x0940c, 0x02000001); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 121 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 122 | /* Configure max ilde count */ |
| 123 | gtt_write(0x02054, 0x0000000a); |
| 124 | gtt_write(0x12054, 0x0000000a); |
| 125 | gtt_write(0x22054, 0x0000000a); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 126 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 127 | gtt_write(0x0a008, 0x10000000); |
| 128 | gtt_write(0x0a024, 0x00000b92); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 129 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 130 | /* Enable RC6 in idle */ |
| 131 | gtt_write(0x0a094, 0x00040000); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 132 | } |
| 133 | |
| 134 | static void gma_pm_init_post_vbios(struct device *dev) |
| 135 | { |
| 136 | struct northbridge_intel_haswell_config *conf = dev->chip_info; |
| 137 | u32 reg32; |
| 138 | |
| 139 | printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); |
| 140 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 141 | /* Disable Force Wake */ |
| 142 | gtt_write(0x0a188, 0x00010000); |
| 143 | gtt_poll(0x130044, 1 << 0, 0 << 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 144 | |
| 145 | /* Setup Digital Port Hotplug */ |
| 146 | reg32 = gtt_read(0xc4030); |
| 147 | if (!reg32) { |
| 148 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 149 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 150 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
| 151 | gtt_write(0xc4030, reg32); |
| 152 | } |
| 153 | |
| 154 | /* Setup Panel Power On Delays */ |
| 155 | reg32 = gtt_read(0xc7208); |
| 156 | if (!reg32) { |
| 157 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 158 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 159 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 160 | gtt_write(0xc7208, reg32); |
| 161 | } |
| 162 | |
| 163 | /* Setup Panel Power Off Delays */ |
| 164 | reg32 = gtt_read(0xc720c); |
| 165 | if (!reg32) { |
| 166 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 167 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 168 | gtt_write(0xc720c, reg32); |
| 169 | } |
| 170 | |
| 171 | /* Setup Panel Power Cycle Delay */ |
| 172 | if (conf->gpu_panel_power_cycle_delay) { |
| 173 | reg32 = gtt_read(0xc7210); |
| 174 | reg32 &= ~0xff; |
| 175 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
| 176 | gtt_write(0xc7210, reg32); |
| 177 | } |
| 178 | |
| 179 | /* Enable Backlight if needed */ |
| 180 | if (conf->gpu_cpu_backlight) { |
| 181 | gtt_write(0x48250, (1 << 31)); |
| 182 | gtt_write(0x48254, conf->gpu_cpu_backlight); |
| 183 | } |
| 184 | if (conf->gpu_pch_backlight) { |
| 185 | gtt_write(0xc8250, (1 << 31)); |
| 186 | gtt_write(0xc8254, conf->gpu_pch_backlight); |
| 187 | } |
| 188 | } |
| 189 | |
| 190 | static void gma_func0_init(struct device *dev) |
| 191 | { |
| 192 | u32 reg32; |
| 193 | |
| 194 | /* IGD needs to be Bus Master */ |
| 195 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 196 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 197 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 198 | |
| 199 | /* Init graphics power management */ |
| 200 | gma_pm_init_pre_vbios(dev); |
| 201 | |
| 202 | /* PCI Init, will run VBIOS */ |
| 203 | pci_dev_init(dev); |
| 204 | |
| 205 | /* Post VBIOS init */ |
| 206 | gma_pm_init_post_vbios(dev); |
| 207 | } |
| 208 | |
| 209 | static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 210 | { |
| 211 | if (!vendor || !device) { |
| 212 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 213 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 214 | } else { |
| 215 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 216 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 217 | } |
| 218 | } |
| 219 | |
Aaron Durbin | fcfe67c | 2013-03-22 22:23:05 -0500 | [diff] [blame] | 220 | static void gma_read_resources(struct device *dev) |
| 221 | { |
| 222 | pci_dev_read_resources(dev); |
| 223 | |
| 224 | #if CONFIG_MARK_GRAPHICS_MEM_WRCOMB |
| 225 | struct resource *res; |
| 226 | |
| 227 | /* Set the graphics memory to write combining. */ |
| 228 | res = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 229 | if (res == NULL) { |
| 230 | printk(BIOS_DEBUG, "gma: memory resource not found.\n"); |
| 231 | return; |
| 232 | } |
| 233 | res->flags |= IORESOURCE_WRCOMB; |
| 234 | #endif |
| 235 | } |
| 236 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 237 | static struct pci_operations gma_pci_ops = { |
| 238 | .set_subsystem = gma_set_subsystem, |
| 239 | }; |
| 240 | |
| 241 | static struct device_operations gma_func0_ops = { |
Aaron Durbin | fcfe67c | 2013-03-22 22:23:05 -0500 | [diff] [blame] | 242 | .read_resources = gma_read_resources, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 243 | .set_resources = pci_dev_set_resources, |
| 244 | .enable_resources = pci_dev_enable_resources, |
| 245 | .init = gma_func0_init, |
| 246 | .scan_bus = 0, |
| 247 | .enable = 0, |
| 248 | .ops_pci = &gma_pci_ops, |
| 249 | }; |
| 250 | |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 251 | static const unsigned short pci_device_ids[] = { |
| 252 | 0x0402, /* Desktop GT1 */ |
| 253 | 0x0412, /* Desktop GT2 */ |
| 254 | 0x0422, /* Desktop GT3 */ |
| 255 | 0x0406, /* Mobile GT1 */ |
| 256 | 0x0416, /* Mobile GT2 */ |
| 257 | 0x0426, /* Mobile GT3 */ |
| 258 | 0x0d16, /* Mobile 4+3 GT1 */ |
| 259 | 0x0d26, /* Mobile 4+3 GT2 */ |
| 260 | 0x0d36, /* Mobile 4+3 GT3 */ |
| 261 | 0x0a06, /* ULT GT1 */ |
| 262 | 0x0a16, /* ULT GT2 */ |
| 263 | 0x0a26, /* ULT GT3 */ |
| 264 | 0, |
| 265 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 266 | |
| 267 | static const struct pci_driver pch_lpc __pci_driver = { |
| 268 | .ops = &gma_func0_ops, |
| 269 | .vendor = PCI_VENDOR_ID_INTEL, |
| 270 | .devices = pci_device_ids, |
| 271 | }; |