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Alexandru Gagniuc23211b02013-06-09 16:06:07 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Alexandru Gagniuc23211b02013-06-09 16:06:07 -050015 */
16
17struct northbridge_via_vx900_config {
18 /**
19 * \brief PCIe Lane[3:0] Function Select
20 *
21 * PCIe Lane3~Lane0 (PEXTX[3:0]P/VCC) can be used by the integrated
22 * graphic controller to output its display data. The PCIe lanes will
23 * be used to output DisplayPort data.
24 */
25 u8 assign_pex_to_dp;
26
27 /**
28 * \brief Lane Width for Root Port 1
29 *
30 * Two PCIe lanes are used for Root port 1. Root port 2 is disabled.
31 */
32 u8 pcie_port1_2_lane_wide;
33
34 /**
35 * \brief PIRQ line to which to route the external interrupt
36 *
37 * The VX900 features an external interrupt which can be routed to any
38 * of the PIRQA->PIRQH lines. Usually, on-board devices are connected
39 * to the external interrupt. In some vendor BIOS's pirq table, this
40 * appears as link 9.
41 *
42 * Setting this line only affects the behavior of the integrated PIC. It
43 * has no effect on the IOAPIC.
44 *
45 * The value of this register must be a literal upper-case character
46 * from 'A' to 'H'.
47 */
48 char ext_int_route_to_pirq;
49};