blob: 2a8d0ea04dc8fb0815d3281063c49a30384f3ba9 [file] [log] [blame]
Kerry Sheh6b909f22012-02-07 20:31:40 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Kerry Sheh6b909f22012-02-07 20:31:40 +080014 */
15
16#ifndef _NB_PLATFORM_H_
17#define _NB_PLATFORM_H_
18
19#define SERIAL_OUT_SUPPORT //enable serial output
20#define CIMX_DEBUG
21
22#ifdef CIMX_DEBUG
23#define CIMX_TRACE_SUPPORT
24#define CIMX_ASSERT_SUPPORT
25#endif
26
27#ifdef CIMX_TRACE_SUPPORT
28 #define CIMX_INIT_TRACE(Arguments)
29 #if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL
30 #define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable
31 #define CIMX_TRACE(Argument) do {do_printk Argument;} while (0)
32 #else
33 #define TRACE_DATA(Ptr, Level)
34 #define CIMX_TRACE(Argument)
35 #endif
36#else
37 #define CIMX_TRACE(Argument)
38 #define CIMX_INIT_TRACE(Arguments)
39#endif
40
41#ifdef CIMX_ASSERT_SUPPORT
42 #ifdef ASSERT
43 #undef ASSERT
44 #define ASSERT CIMX_ASSERT
45 #endif
46 #ifdef CIMX_TRACE_SUPPORT
47 #define CIMX_ASSERT(x) if(!(x)) {\
48 LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \
49 /*__asm {jmp $}; */\
50 }
51 //#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args)
52 #else
53 #define CIMX_ASSERT(x) if(!(x)) {\
54 /*__asm {jmp $}; */\
55 }
56 #endif
57#else
58 #define CIMX_ASSERT(x)
59#endif
60
61/*----------------------------------------------------------------------------------------
62 * E X P O R T E D F U N C T I O N S
63 *----------------------------------------------------------------------------------------
64 */
65
66//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs)
67#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr)
68
69#ifdef B2_IMAGE
70#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) LibNbEventLog(Class, Info, Param1, Param2, Param3, Param4, CfgPtr)
71#else
72#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr)
73#endif
74
75
76
77// CIMX configuration parameters
78//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000
Martin Rothf4cb4122015-01-06 10:27:39 -070079/*
80 * PCIEX_BASE_ADDRESS - Define PCIE base address
Kerry Sheh6b909f22012-02-07 20:31:40 +080081 */
82#ifdef MOVE_PCIEBAR_TO_F0000000
83#define PCIEX_BASE_ADDRESS 0xF7000000
84#else
85#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
86#endif
87
88
89
90#define CIMX_S3_SAVE 1
Vikram Narayanan2f00ce32012-04-21 23:47:56 +053091#include <cpu/amd/common/cbtypes.h>
Kerry Sheh6b909f22012-02-07 20:31:40 +080092#include <console/console.h>
93
94#include "amd.h" //cimx typedef
95#include <amdlib.h>
96#include "amdAcpiLib.h"
97#include "amdAcpiMadt.h"
98#include "amdAcpiIvrs.h"
99#include "amdSbLib.h"
100#include "nbPcie.h"
101
102//must put before the nbType.h
103#include "platform_cfg.h" /*platform dependented configuration */
104#include "nbType.h"
105
106#include "nbLib.h"
107#include "nbDef.h"
108#include "nbInit.h"
109#include "nbHtInit.h"
110#include "nbIommu.h"
111#include "nbEventLog.h"
112#include "nbRegisters.h"
113#include "nbPcieAspm.h"
114#include "nbPcieLinkWidth.h"
115#include "nbPcieHotplug.h"
116#include "nbPciePortRemap.h"
117#include "nbPcieWorkarounds.h"
118#include "nbPcieCplBuffers.h"
119#include "nbPciePllControl.h"
120#include "nbMiscInit.h"
121#include "nbIoApic.h"
122#include "nbPcieSb.h"
123#include "nbRecovery.h"
124#include "nbMaskedMemoryInit.h"
125
126
127#define FIX_PTR_ADDR(x, y) x
128
129#define TRACE_ALWAYS 0xffffffff
130
131#define AmdNbDispatcher NULL
132
133#define CIMX_TRACE_ALL 0xFFFFFFFF
134#define CIMX_NBPOR_TRACE 0xFFFFFFFF
135#define CIMX_NBHT_TRACE 0xFFFFFFFF
136#define CIMX_NBPCIE_TRACE 0xFFFFFFFF
137#define CIMX_NB_TRACE 0xFFFFFFFF
138#define CIMX_NBPCIE_MISC 0xFFFFFFFF
139
140#endif