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review.coreboot.org / coreboot / 2a3434757ef425dbdfedf1fc69e1a033a6e7310d / . / src / console / Kconfig
blob: 90fb426cee0d281c6ec7adba68d82e3e75427b4f [file] [log] [blame]
Stefan Reinauer1b342262011-01-05 02:27:53 +0000[diff] [blame]1menu "Console"
Hung-Te Linad173ea2013-02-06 21:24:12 +0800[diff] [blame]2
Gabe Blackfbb11cf2013-06-06 00:21:20 -0700[diff] [blame]3config BOOTBLOCK_CONSOLE
4 bool "Enable early (bootblock) console output."
Alexandru Gagniucee464b12015-10-02 18:01:18 -0700[diff] [blame]5 depends on C_ENVIRONMENT_BOOTBLOCK
Stefan Reinauerd2f45c62013-06-19 13:42:00 -0700[diff] [blame]6 default n
Gabe Blackfbb11cf2013-06-06 00:21:20 -0700[diff] [blame]7 help
8 Use console during the bootblock if supported
9
Kyösti Mälkki361cd812013-08-12 23:29:57 +0300[diff] [blame]10config SQUELCH_EARLY_SMP
11 bool "Squelch AP CPUs from early console."
12 default y
Lee Leahyf2ad50fe2016-02-08 16:19:56 -0800[diff] [blame]13 depends on SMP
Kyösti Mälkki361cd812013-08-12 23:29:57 +0300[diff] [blame]14 help
15 When selected only the BSP CPU will output to early console.
16
17 Console drivers have unpredictable behaviour if multiple threads
18 attempt to share the same resources without a spinlock.
19
20 If unsure, say Y.
21
Hung-Te Linad173ea2013-02-06 21:24:12 +0800[diff] [blame]22config CONSOLE_SERIAL
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]23 bool "Serial port console output"
Stefan Reinauer509f7722012-12-07 17:31:37 -0800[diff] [blame]24 default y
Kyösti Mälkkiafa7b132014-02-13 17:16:22 +0200[diff] [blame]25 depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL
Stefan Reinauer509f7722012-12-07 17:31:37 -0800[diff] [blame]26 help
Kyösti Mälkkiafa7b132014-02-13 17:16:22 +0200[diff] [blame]27 Send coreboot debug output to a serial port.
David Hendricks6a503b62012-12-31 17:28:43 -0800[diff] [blame]28
Kyösti Mälkkiafa7b132014-02-13 17:16:22 +0200[diff] [blame]29 The type of serial port driver selected based on your configuration is
30 shown on the following menu line. Supporting multiple different types
31 of UARTs in one build is not supported.
Stefan Reinauer4885daa2011-04-26 23:47:04 +0000[diff] [blame]32
Kyösti Mälkkiafa7b132014-02-13 17:16:22 +0200[diff] [blame]33if CONSOLE_SERIAL
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]34
Kyösti Mälkkiafa7b132014-02-13 17:16:22 +0200[diff] [blame]35 comment "I/O mapped, 8250-compatible"
36 depends on DRIVERS_UART_8250IO
37
38 comment "memory mapped, 8250-compatible"
39 depends on DRIVERS_UART_8250MEM
40
41 comment "device-specific UART"
Hung-Te Linad173ea2013-02-06 21:24:12 +0800[diff] [blame]42 depends on HAVE_UART_SPECIAL
Stefan Reinauer509f7722012-12-07 17:31:37 -0800[diff] [blame]43
Kyösti Mälkki70342a72014-03-14 22:28:29 +0200[diff] [blame]44config UART_FOR_CONSOLE
Kyösti Mälkkid5403772014-05-01 00:02:43 +0300[diff] [blame]45 int "Index for UART port to use for console"
Kyösti Mälkki70342a72014-03-14 22:28:29 +0200[diff] [blame]46 default 0
Martin Rothac76ed92015-11-19 11:40:43 -0700[diff] [blame]47 help
48 Select an I/O port to use for serial console:
49 0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]50
Kyösti Mälkki70342a72014-03-14 22:28:29 +0200[diff] [blame]51# FIXME: Early programming in romstage is incorrect as we should
52# program different LDN to actually change the physical port.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]53config TTYS0_BASE
54 hex
Gabe Black77ffa0d2013-09-30 21:25:49 -0700[diff] [blame]55 depends on DRIVERS_UART
Kyösti Mälkki70342a72014-03-14 22:28:29 +0200[diff] [blame]56 default 0x3f8 if UART_FOR_CONSOLE = 0
57 default 0x2f8 if UART_FOR_CONSOLE = 1
58 default 0x3e8 if UART_FOR_CONSOLE = 2
59 default 0x2e8 if UART_FOR_CONSOLE = 3
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]60 help
Kyösti Mälkki70342a72014-03-14 22:28:29 +0200[diff] [blame]61 Map the COM port number to the respective I/O port.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]62
Martin Rothac76ed92015-11-19 11:40:43 -0700[diff] [blame]63comment "Serial port base address = 0x3f8"
64depends on UART_FOR_CONSOLE = 0
65comment "Serial port base address = 0x2f8"
66depends on UART_FOR_CONSOLE = 1
67comment "Serial port base address = 0x3e8"
68depends on UART_FOR_CONSOLE = 2
69comment "Serial port base address = 0x2e8"
70depends on UART_FOR_CONSOLE = 3
71
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]72choice
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]73 prompt "Baud rate"
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]74 default CONSOLE_SERIAL_115200
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]75
Lee Leahycda71b82016-02-20 05:39:10 -0800[diff] [blame]76config CONSOLE_SERIAL_921600
77 bool "921600"
78 help
79 Set serial port Baud rate to 921600.
80config CONSOLE_SERIAL_460800
81 bool "460800"
82 help
83 Set serial port Baud rate to 460800.
84config CONSOLE_SERIAL_230400
85 bool "230400"
86 help
87 Set serial port Baud rate to 230400.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]88config CONSOLE_SERIAL_115200
89 bool "115200"
90 help
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]91 Set serial port Baud rate to 115200.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]92config CONSOLE_SERIAL_57600
93 bool "57600"
94 help
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]95 Set serial port Baud rate to 57600.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]96config CONSOLE_SERIAL_38400
97 bool "38400"
98 help
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]99 Set serial port Baud rate to 38400.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]100config CONSOLE_SERIAL_19200
101 bool "19200"
102 help
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]103 Set serial port Baud rate to 19200.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]104config CONSOLE_SERIAL_9600
105 bool "9600"
106 help
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]107 Set serial port Baud rate to 9600.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]108
109endchoice
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]110
Stefan Reinauer509f7722012-12-07 17:31:37 -0800[diff] [blame]111#FIXME(dhendrix): Change name to SERIAL_BAUD? (Stefan sayz: yes!!)
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]112config TTYS0_BAUD
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]113 int
Lee Leahycda71b82016-02-20 05:39:10 -0800[diff] [blame]114 default 921600 if CONSOLE_SERIAL_921600
115 default 460800 if CONSOLE_SERIAL_460800
116 default 230400 if CONSOLE_SERIAL_230400
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]117 default 115200 if CONSOLE_SERIAL_115200
118 default 57600 if CONSOLE_SERIAL_57600
119 default 38400 if CONSOLE_SERIAL_38400
120 default 19200 if CONSOLE_SERIAL_19200
121 default 9600 if CONSOLE_SERIAL_9600
122 help
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]123 Map the Baud rates to an integer.
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]124
Uwe Hermann168b11b2009-10-07 16:15:40 +0000[diff] [blame]125# TODO: Allow user-friendly selection of settings other than 8n1.
Patrick Georgi0e9a9252009-10-06 20:48:07 +0000[diff] [blame]126config TTYS0_LCS
127 int
128 default 3
Kyösti Mälkkiafa7b132014-02-13 17:16:22 +0200[diff] [blame]129 depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM
130
131endif # CONSOLE_SERIAL
Patrick Georgi0e9a9252009-10-06 20:48:07 +0000[diff] [blame]132
Vladimir Serbinenko45988da2013-03-30 02:02:13 +0100[diff] [blame]133config SPKMODEM
134 bool "spkmodem (console on speaker) console output"
135 default n
Vladimir Serbinenkod51a0892016-03-04 09:20:20 +0100[diff] [blame]136 depends on ARCH_X86
Vladimir Serbinenko45988da2013-03-30 02:02:13 +0100[diff] [blame]137 help
138 Send coreboot debug output through speaker
139
Kyösti Mälkkiab94bbf2014-02-25 12:06:14 +0200[diff] [blame]140config CONSOLE_USB
141 bool "USB dongle console output"
142 depends on USBDEBUG
Kyösti Mälkki8101aa62013-08-15 16:27:06 +0300[diff] [blame]143 default n
Uwe Hermann168b11b2009-10-07 16:15:40 +0000[diff] [blame]144 help
Kyösti Mälkkiab94bbf2014-02-25 12:06:14 +0200[diff] [blame]145 Send coreboot debug output to USB.
Uwe Hermann168b11b2009-10-07 16:15:40 +0000[diff] [blame]146
Kyösti Mälkkiab94bbf2014-02-25 12:06:14 +0200[diff] [blame]147 Configuration for USB hardware is under menu Generic Drivers.
Kyösti Mälkkid2dac0a2013-08-23 23:33:16 +0300[diff] [blame]148
Uwe Hermann168b11b2009-10-07 16:15:40 +0000[diff] [blame]149# TODO: Deps?
150# TODO: Improve description.
Stefan Reinauerabc0c852010-11-22 08:09:50 +0000[diff] [blame]151config ONBOARD_VGA_IS_PRIMARY
Uwe Hermann168b11b2009-10-07 16:15:40 +0000[diff] [blame]152 bool "Use onboard VGA as primary video device"
Myles Watson45bb25f2009-09-22 18:49:08 +0000[diff] [blame]153 default n
Vladimir Serbinenkod51a0892016-03-04 09:20:20 +0100[diff] [blame]154 depends on PCI
Myles Watson45bb25f2009-09-22 18:49:08 +0000[diff] [blame]155 help
156 If not selected, the last adapter found will be used.
157
Rudolf Marek4aa93cc2010-07-16 20:02:09 +0000[diff] [blame]158config CONSOLE_NE2K
159 bool "Network console over NE2000 compatible Ethernet adapter"
160 default n
Vladimir Serbinenkod51a0892016-03-04 09:20:20 +0100[diff] [blame]161 depends on PCI
Rudolf Marek4aa93cc2010-07-16 20:02:09 +0000[diff] [blame]162 help
163 Send coreboot debug output to a Ethernet console, it works
164 same way as Linux netconsole, packets are received to UDP
165 port 6666 on IP/MAC specified with options bellow.
166 Use following netcat command: nc -u -l -p 6666
167
168config CONSOLE_NE2K_DST_MAC
169 depends on CONSOLE_NE2K
170 string "Destination MAC address of remote system"
171 default "00:13:d4:76:a2:ac"
172 help
173 Type in either MAC address of logging system or MAC address
174 of the router.
175
176config CONSOLE_NE2K_DST_IP
177 depends on CONSOLE_NE2K
178 string "Destination IP of logging system"
179 default "10.0.1.27"
180 help
Daniele Forsi53847a22014-07-22 18:00:56 +0200[diff] [blame]181 This is IP address of the system running for example
Rudolf Marek4aa93cc2010-07-16 20:02:09 +0000[diff] [blame]182 netcat command to dump the packets.
183
184config CONSOLE_NE2K_SRC_IP
185 depends on CONSOLE_NE2K
Stefan Reinauerd6b4f1c2010-09-23 18:29:40 +0000[diff] [blame]186 string "IP address of coreboot system"
Rudolf Marek4aa93cc2010-07-16 20:02:09 +0000[diff] [blame]187 default "10.0.1.253"
188 help
Stefan Reinauerd6b4f1c2010-09-23 18:29:40 +0000[diff] [blame]189 This is the IP of the coreboot system
Rudolf Marek4aa93cc2010-07-16 20:02:09 +0000[diff] [blame]190
191config CONSOLE_NE2K_IO_PORT
192 depends on CONSOLE_NE2K
193 hex "NE2000 adapter fixed IO port address"
194 default 0xe00
195 help
196 This is the IO port address for the IO port
197 on the card, please select some non-conflicting region,
198 32 bytes of IO spaces will be used (and align on 32 bytes
199 boundary, qemu needs broader align)
200
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]201config CONSOLE_CBMEM
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]202 bool "Send console output to a CBMEM buffer"
Paul Menzel60ef4562014-03-08 10:46:52 +0100[diff] [blame]203 default y
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]204 help
205 Enable this to save the console output in a CBMEM buffer. This would
206 allow to see coreboot console output from Linux space.
207
Kyösti Mälkki8659e402014-12-21 08:55:47 +0200[diff] [blame]208if CONSOLE_CBMEM
209
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]210config CONSOLE_CBMEM_BUFFER_SIZE
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]211 hex "Room allocated for console output in CBMEM"
Vladimir Serbinenkoeb67a042014-09-13 20:55:58 +0200[diff] [blame]212 default 0x20000
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]213 help
214 Space allocated for console output storage in CBMEM. The default
Vladimir Serbinenkoeb67a042014-09-13 20:55:58 +0200[diff] [blame]215 value (128K or 0x20000 bytes) is large enough to accommodate
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]216 even the BIOS_SPEW level.
217
Vadim Bendebury6e20e2f2015-04-10 18:04:04 -0700[diff] [blame]218config CONSOLE_CBMEM_DUMP_TO_UART
219 depends on !CONSOLE_SERIAL
220 bool "Dump CBMEM console on resets"
221 default n
222 help
223 Enable this to have CBMEM console buffer contents dumped on the
224 serial output in case serial console is disabled and the device
225 resets itself while trying to boot the payload.
226
Kyösti Mälkki8659e402014-12-21 08:55:47 +0200[diff] [blame]227endif
228
Gerd Hoffmannd7c6e442013-05-30 10:32:31 +0200[diff] [blame]229config CONSOLE_QEMU_DEBUGCON
Gerd Hoffmann038aa292013-05-29 13:06:22 +0200[diff] [blame]230 bool "QEMU debug console output"
231 depends on BOARD_EMULATION_QEMU_X86
232 default y
233 help
234 Send coreboot debug output to QEMU's isa-debugcon device:
235
236 qemu-system-x86_64 \
237 -chardev file,id=debugcon,path=/dir/file.log \
238 -device isa-debugcon,iobase=0x402,chardev=debugcon
239
Gerd Hoffmannd7c6e442013-05-30 10:32:31 +0200[diff] [blame]240config CONSOLE_QEMU_DEBUGCON_PORT
Gerd Hoffmann038aa292013-05-29 13:06:22 +0200[diff] [blame]241 hex "QEMU debug console port"
Gerd Hoffmannd7c6e442013-05-30 10:32:31 +0200[diff] [blame]242 depends on CONSOLE_QEMU_DEBUGCON
Gerd Hoffmann038aa292013-05-29 13:06:22 +0200[diff] [blame]243 default 0x402
244
Martin Roth3a543182015-09-28 15:27:24 -0600[diff] [blame]245config SPI_CONSOLE
246 bool "SPI debug console output"
247 depends on HAVE_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH
248 help
249 Enable support for the debug console on the Dediprog EM100Pro.
250 This is currently working only in ramstage due to how the spi
251 drivers are written.
252
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]253choice
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]254 prompt "Default console log level"
255 default DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]256
257config DEFAULT_CONSOLE_LOGLEVEL_8
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]258 bool "8: SPEW"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]259 help
260 Way too many details.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]261config DEFAULT_CONSOLE_LOGLEVEL_7
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]262 bool "7: DEBUG"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]263 help
264 Debug-level messages.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]265config DEFAULT_CONSOLE_LOGLEVEL_6
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]266 bool "6: INFO"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]267 help
268 Informational messages.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]269config DEFAULT_CONSOLE_LOGLEVEL_5
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]270 bool "5: NOTICE"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]271 help
272 Normal but significant conditions.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]273config DEFAULT_CONSOLE_LOGLEVEL_4
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]274 bool "4: WARNING"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]275 help
276 Warning conditions.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]277config DEFAULT_CONSOLE_LOGLEVEL_3
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]278 bool "3: ERR"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]279 help
280 Error conditions.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]281config DEFAULT_CONSOLE_LOGLEVEL_2
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]282 bool "2: CRIT"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]283 help
284 Critical conditions.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]285config DEFAULT_CONSOLE_LOGLEVEL_1
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]286 bool "1: ALERT"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]287 help
288 Action must be taken immediately.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]289config DEFAULT_CONSOLE_LOGLEVEL_0
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]290 bool "0: EMERG"
291 help
292 System is unusable.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]293
294endchoice
295
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]296config DEFAULT_CONSOLE_LOGLEVEL
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]297 int
298 default 0 if DEFAULT_CONSOLE_LOGLEVEL_0
299 default 1 if DEFAULT_CONSOLE_LOGLEVEL_1
300 default 2 if DEFAULT_CONSOLE_LOGLEVEL_2
301 default 3 if DEFAULT_CONSOLE_LOGLEVEL_3
302 default 4 if DEFAULT_CONSOLE_LOGLEVEL_4
303 default 5 if DEFAULT_CONSOLE_LOGLEVEL_5
304 default 6 if DEFAULT_CONSOLE_LOGLEVEL_6
305 default 7 if DEFAULT_CONSOLE_LOGLEVEL_7
306 default 8 if DEFAULT_CONSOLE_LOGLEVEL_8
307 help
308 Map the log level config names to an integer.
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]309
Stefan Reinauerc719f1a2010-03-30 09:57:28 +0000[diff] [blame]310config NO_POST
311 bool "Don't show any POST codes"
312 default n
313
Duncan Laurieb6e97b12012-09-09 19:09:56 -0700[diff] [blame]314config CMOS_POST
315 bool "Store post codes in CMOS for debugging"
Stefan Reinauerc2d5a162012-12-06 14:25:27 -0800[diff] [blame]316 depends on !NO_POST && PC80_SYSTEM
Duncan Laurieb6e97b12012-09-09 19:09:56 -0700[diff] [blame]317 default n
318 help
319 If enabled, coreboot will store post codes in CMOS and switch between
320 two offsets on each boot so the last post code in the previous boot
321 can be retrieved. This uses 3 bytes of CMOS.
322
323config CMOS_POST_OFFSET
324 hex "Offset into CMOS to store POST codes"
325 depends on CMOS_POST
326 default 0
327 help
328 If CMOS_POST is enabled then an offset into CMOS must be provided.
329 If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
330 defined in the mainboard option table.
331
Duncan Lauried5686fe2013-06-10 10:21:41 -0700[diff] [blame]332config CMOS_POST_EXTRA
333 bool "Store extra logging info into CMOS"
334 depends on CMOS_POST
335 default n
336 help
337 This will enable extra logging of work that happens between post
338 codes into CMOS for debug. This uses an additional 8 bytes of CMOS.
339
Daniele Forsiad488d22014-07-30 12:23:35 +0200[diff] [blame]340config CONSOLE_POST
Idwer Vollering5809a732014-03-11 15:36:21 +0000[diff] [blame]341 bool "Show POST codes on the debug console"
342 depends on !NO_POST
343 default n
344 help
345 If enabled, coreboot will additionally print POST codes (which are
346 usually displayed using a so-called "POST card" ISA/PCI/PCI-E
347 device) on the debug console.
348
349config POST_DEVICE
350 bool "Send POST codes to an external device"
351 depends on !NO_POST
352 default y
353
354choice
355 prompt "Device to send POST codes to"
356 depends on POST_DEVICE
357 default POST_DEVICE_NONE
358
359config POST_DEVICE_NONE
360 bool "None"
361config POST_DEVICE_LPC
362 bool "LPC"
Vladimir Serbinenkod51a0892016-03-04 09:20:20 +0100[diff] [blame]363 depends on PCI
Idwer Vollering5809a732014-03-11 15:36:21 +0000[diff] [blame]364config POST_DEVICE_PCI_PCIE
365 bool "PCI/PCIe"
Vladimir Serbinenkod51a0892016-03-04 09:20:20 +0100[diff] [blame]366 depends on PCI
Idwer Vollering5809a732014-03-11 15:36:21 +0000[diff] [blame]367endchoice
368
369config POST_IO
David Hendricks6b908d02012-11-05 12:34:09 -0800[diff] [blame]370 bool "Send POST codes to an IO port"
Idwer Vollering5809a732014-03-11 15:36:21 +0000[diff] [blame]371 depends on PC80_SYSTEM && !NO_POST
David Hendricks6b908d02012-11-05 12:34:09 -0800[diff] [blame]372 default y
373 help
374 If enabled, POST codes will be written to an IO port.
Stefan Reinauerc719f1a2010-03-30 09:57:28 +0000[diff] [blame]375
Idwer Vollering5809a732014-03-11 15:36:21 +0000[diff] [blame]376config POST_IO_PORT
377 depends on POST_IO
David Hendricks6b908d02012-11-05 12:34:09 -0800[diff] [blame]378 hex "IO port for POST codes"
379 default 0x80
380 help
381 POST codes on x86 are typically written to the LPC bus on port
Daniele Forsi53847a22014-07-22 18:00:56 +0200[diff] [blame]382 0x80. However, it may be desirable to change the port number
David Hendricks6b908d02012-11-05 12:34:09 -0800[diff] [blame]383 depending on the presence of coprocessors/microcontrollers or if the
384 platform does not support IO in the conventional x86 manner.
385
Martin Roth14554372015-11-12 14:02:42 -0700[diff] [blame]386config NO_EARLY_BOOTBLOCK_POSTCODES
387 def_bool n
388 help
389 Some chipsets require that the routing for the port 80h POST
390 code be configured before any POST codes are sent out.
391 This can be done in the boot block, but there are a couple of
392 POST codes that go out before the chipset's bootblock initialization
393 can happen. This option suppresses those POST codes.
394
David Hendricks6b908d02012-11-05 12:34:09 -0800[diff] [blame]395endmenu