Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * inteltool - dump all registers on an Intel CPU + chipset based system. |
| 3 | * |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 4 | * Copyright (C) 2008-2010 by coresystems GmbH |
Idwer Vollering | 3f91d81 | 2010-10-24 13:50:13 +0000 | [diff] [blame] | 5 | * Copyright (C) 2009 Carl-Daniel Hailfinger |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 6 | * |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 22 | |
| 23 | #if defined(__GLIBC__) |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 24 | #include <sys/io.h> |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 25 | #endif |
| 26 | #if (defined(__MACH__) && defined(__APPLE__)) |
Stefan Reinauer | 4cf7879 | 2011-03-18 22:53:38 +0000 | [diff] [blame] | 27 | /* DirectHW is available here: http://www.coreboot.org/DirectHW */ |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 28 | #define __DARWIN__ |
Stefan Reinauer | cff573d | 2011-03-18 22:08:39 +0000 | [diff] [blame] | 29 | #include <DirectHW/DirectHW.h> |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 30 | #endif |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 31 | #include <pci/pci.h> |
| 32 | |
Idwer Vollering | 3f91d81 | 2010-10-24 13:50:13 +0000 | [diff] [blame] | 33 | /* This #include is needed for freebsd_{rd,wr}msr. */ |
| 34 | #if defined(__FreeBSD__) |
| 35 | #include <machine/cpufunc.h> |
| 36 | #endif |
| 37 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 38 | #define INTELTOOL_VERSION "1.0" |
| 39 | |
| 40 | /* Tested chipsets: */ |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 41 | #define PCI_VENDOR_ID_INTEL 0x8086 |
| 42 | #define PCI_DEVICE_ID_INTEL_ICH 0x2410 |
| 43 | #define PCI_DEVICE_ID_INTEL_ICH0 0x2420 |
| 44 | #define PCI_DEVICE_ID_INTEL_ICH2 0x2440 |
| 45 | #define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 |
| 46 | #define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 47 | #define PCI_DEVICE_ID_INTEL_ICH5 0x24d0 |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 48 | #define PCI_DEVICE_ID_INTEL_ICH6 0x2640 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 49 | #define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 |
| 50 | #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 |
| 51 | #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 |
| 52 | #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd |
Corey Osgood | f366ce0 | 2010-08-17 08:33:44 +0000 | [diff] [blame] | 53 | #define PCI_DEVICE_ID_INTEL_NM10 0x27bc |
| 54 | #define PCI_DEVICE_ID_INTEL_ICH8 0x2810 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 55 | #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 |
Anton Kochkov | da0b456 | 2010-05-30 12:33:12 +0000 | [diff] [blame] | 56 | #define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912 |
| 57 | #define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914 |
| 58 | #define PCI_DEVICE_ID_INTEL_ICH9R 0x2916 |
| 59 | #define PCI_DEVICE_ID_INTEL_ICH9 0x2918 |
| 60 | #define PCI_DEVICE_ID_INTEL_ICH9M 0x2919 |
| 61 | #define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 62 | #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 |
Stefan Tauner | 088f569 | 2013-05-28 11:30:25 +0200 | [diff] [blame] | 63 | #define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00 |
| 64 | #define PCI_DEVICE_ID_INTEL_3400_MOBILE 0x3b01 |
| 65 | #define PCI_DEVICE_ID_INTEL_P55 0x3b02 |
| 66 | #define PCI_DEVICE_ID_INTEL_PM55 0x3b03 |
| 67 | #define PCI_DEVICE_ID_INTEL_H55 0x3b06 |
| 68 | #define PCI_DEVICE_ID_INTEL_QM57 0x3b07 |
| 69 | #define PCI_DEVICE_ID_INTEL_H57 0x3b08 |
| 70 | #define PCI_DEVICE_ID_INTEL_HM55 0x3b09 |
| 71 | #define PCI_DEVICE_ID_INTEL_Q57 0x3b0a |
| 72 | #define PCI_DEVICE_ID_INTEL_HM57 0x3b0b |
| 73 | #define PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF 0x3b0d |
| 74 | #define PCI_DEVICE_ID_INTEL_B55_A 0x3b0e |
| 75 | #define PCI_DEVICE_ID_INTEL_QS57 0x3b0f |
| 76 | #define PCI_DEVICE_ID_INTEL_3400 0x3b12 |
| 77 | #define PCI_DEVICE_ID_INTEL_3420 0x3b14 |
| 78 | #define PCI_DEVICE_ID_INTEL_3450 0x3b16 |
| 79 | #define PCI_DEVICE_ID_INTEL_B55_B 0x3b1e |
Stefan Reinauer | 74cd5698 | 2010-06-01 10:04:28 +0000 | [diff] [blame] | 80 | #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 |
Nico Huber | 76d6049 | 2013-03-29 17:57:15 +0100 | [diff] [blame] | 81 | #define PCI_DEVICE_ID_INTEL_Z68 0x1c44 |
| 82 | #define PCI_DEVICE_ID_INTEL_P67 0x1c46 |
| 83 | #define PCI_DEVICE_ID_INTEL_UM67 0x1c47 |
| 84 | #define PCI_DEVICE_ID_INTEL_HM65 0x1c49 |
| 85 | #define PCI_DEVICE_ID_INTEL_H67 0x1c4a |
| 86 | #define PCI_DEVICE_ID_INTEL_HM67 0x1c4b |
| 87 | #define PCI_DEVICE_ID_INTEL_Q65 0x1c4c |
| 88 | #define PCI_DEVICE_ID_INTEL_QS67 0x1c4d |
| 89 | #define PCI_DEVICE_ID_INTEL_Q67 0x1c4e |
| 90 | #define PCI_DEVICE_ID_INTEL_QM67 0x1c4f |
| 91 | #define PCI_DEVICE_ID_INTEL_B65 0x1c50 |
| 92 | #define PCI_DEVICE_ID_INTEL_C202 0x1c52 |
| 93 | #define PCI_DEVICE_ID_INTEL_C204 0x1c54 |
| 94 | #define PCI_DEVICE_ID_INTEL_C206 0x1c56 |
| 95 | #define PCI_DEVICE_ID_INTEL_H61 0x1c5c |
| 96 | #define PCI_DEVICE_ID_INTEL_Z77 0x1e44 |
| 97 | #define PCI_DEVICE_ID_INTEL_Z75 0x1e46 |
| 98 | #define PCI_DEVICE_ID_INTEL_Q77 0x1e47 |
| 99 | #define PCI_DEVICE_ID_INTEL_Q75 0x1e48 |
| 100 | #define PCI_DEVICE_ID_INTEL_B75 0x1e49 |
| 101 | #define PCI_DEVICE_ID_INTEL_H77 0x1e4a |
| 102 | #define PCI_DEVICE_ID_INTEL_C216 0x1e53 |
| 103 | #define PCI_DEVICE_ID_INTEL_QM77 0x1e55 |
| 104 | #define PCI_DEVICE_ID_INTEL_QS77 0x1e56 |
| 105 | #define PCI_DEVICE_ID_INTEL_HM77 0x1e57 |
| 106 | #define PCI_DEVICE_ID_INTEL_UM77 0x1e58 |
| 107 | #define PCI_DEVICE_ID_INTEL_HM76 0x1e59 |
| 108 | #define PCI_DEVICE_ID_INTEL_HM75 0x1e5d |
| 109 | #define PCI_DEVICE_ID_INTEL_HM70 0x1e5e |
| 110 | #define PCI_DEVICE_ID_INTEL_NM70 0x1e5f |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 111 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41 |
| 112 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43 |
| 113 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 114 | #define PCI_DEVICE_ID_INTEL_82810 0x7120 |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 115 | #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 |
| 116 | #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 117 | #define PCI_DEVICE_ID_INTEL_82830M 0x3575 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 118 | #define PCI_DEVICE_ID_INTEL_82845 0x1a30 |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 119 | #define PCI_DEVICE_ID_INTEL_82865 0x2570 |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 120 | #define PCI_DEVICE_ID_INTEL_82915 0x2580 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 121 | #define PCI_DEVICE_ID_INTEL_82945P 0x2770 |
| 122 | #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 123 | #define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac |
Stefan Tauner | 1a00cf0 | 2012-10-13 06:23:52 +0200 | [diff] [blame] | 124 | #define PCI_DEVICE_ID_INTEL_82946 0x2970 |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 125 | #define PCI_DEVICE_ID_INTEL_82965PM 0x2a00 |
| 126 | #define PCI_DEVICE_ID_INTEL_82Q965 0x2990 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 127 | #define PCI_DEVICE_ID_INTEL_82975X 0x277c |
Loïc Grenié | 8429de7 | 2009-11-02 15:01:49 +0000 | [diff] [blame] | 128 | #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0 |
| 129 | #define PCI_DEVICE_ID_INTEL_82G33 0x29c0 |
| 130 | #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 131 | #define PCI_DEVICE_ID_INTEL_82X38 0x29e0 |
Ruud Schramp | bb41f50 | 2011-04-04 07:53:19 +0200 | [diff] [blame] | 132 | #define PCI_DEVICE_ID_INTEL_32X0 0x29f0 |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 133 | #define PCI_DEVICE_ID_INTEL_82X4X 0x2a40 |
| 134 | #define PCI_DEVICE_ID_INTEL_82X58 0x3405 |
| 135 | #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 |
| 136 | #define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 |
Sven Schnelle | 54a5aed | 2011-10-30 13:30:36 +0100 | [diff] [blame] | 137 | #define PCI_DEVICE_ID_INTEL_I63XX 0x2670 |
Sven Schnelle | 4b7b320 | 2012-01-08 15:27:18 +0100 | [diff] [blame] | 138 | |
Sven Schnelle | 56dfc7c | 2012-07-05 22:53:57 +0200 | [diff] [blame] | 139 | #define PCI_DEVICE_ID_INTEL_I5000X 0x25c0 |
| 140 | #define PCI_DEVICE_ID_INTEL_I5000Z 0x25d0 |
| 141 | #define PCI_DEVICE_ID_INTEL_I5000V 0x25d4 |
Sven Schnelle | 4b7b320 | 2012-01-08 15:27:18 +0100 | [diff] [blame] | 142 | #define PCI_DEVICE_ID_INTEL_I5000P 0x25d8 |
| 143 | |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 144 | /* untested, but almost identical to D-series */ |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 145 | #define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 146 | |
| 147 | #define PCI_DEVICE_ID_INTEL_82443LX 0x7180 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 148 | /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ |
| 149 | #define PCI_DEVICE_ID_INTEL_82443BX 0x7190 |
| 150 | #define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192 |
| 151 | |
| 152 | /* 82371AB/EB/MB use the same device ID value. */ |
| 153 | #define PCI_DEVICE_ID_INTEL_82371XX 0x7110 |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 154 | |
Martin Roth | 51dde6f | 2014-12-07 22:11:54 -0700 | [diff] [blame] | 155 | /* Bay Trail */ |
| 156 | #define PCI_DEVICE_ID_INTEL_BAYTRAIL 0x0f00 /* SOC Transaction Router */ |
| 157 | #define PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC 0x0f1c |
| 158 | #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 |
| 159 | #define CPUID_BAYTRAIL 0x30670 |
| 160 | |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 161 | /* Intel starts counting these generations with the integration of the DRAM controller */ |
Stefan Tauner | dbc6fcd | 2013-06-20 18:05:06 +0200 | [diff] [blame] | 162 | #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 163 | #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ |
Felix Held | 0cc8f29 | 2014-11-05 03:18:44 +0100 | [diff] [blame] | 164 | #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */ |
| 165 | #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */ |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 166 | #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3 0x0108 /* Sandy Bridge (Xeon E3) */ |
| 167 | #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D 0x0150 /* Ivy Bridge (Desktop) */ |
| 168 | #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M 0x0154 /* Ivy Bridge (Mobile) */ |
| 169 | #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3 0x0158 /* Ivy Bridge (Xeon E3 v2) */ |
| 170 | #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c 0x015c /* Ivy Bridge (?) */ |
| 171 | #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D 0x0c00 /* Haswell (Desktop) */ |
| 172 | #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */ |
| 173 | #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */ |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 174 | #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 175 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 176 | #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) |
| 177 | |
Idwer Vollering | 3f91d81 | 2010-10-24 13:50:13 +0000 | [diff] [blame] | 178 | #if !defined(__DARWIN__) && !defined(__FreeBSD__) |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 179 | typedef struct { uint32_t hi, lo; } msr_t; |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 180 | #endif |
Idwer Vollering | 3f91d81 | 2010-10-24 13:50:13 +0000 | [diff] [blame] | 181 | #if defined (__FreeBSD__) |
| 182 | /* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */ |
| 183 | #undef rdmsr |
| 184 | #undef wrmsr |
| 185 | #define rdmsr freebsd_rdmsr |
| 186 | #define wrmsr freebsd_wrmsr |
| 187 | typedef struct { uint32_t hi, lo; } msr_t; |
| 188 | msr_t freebsd_rdmsr(int addr); |
| 189 | int freebsd_wrmsr(int addr, msr_t msr); |
| 190 | #endif |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 191 | typedef struct { uint16_t addr; int size; char *name; } io_register_t; |
| 192 | |
Stefan Reinauer | cff573d | 2011-03-18 22:08:39 +0000 | [diff] [blame] | 193 | void *map_physical(uint64_t phys_addr, size_t len); |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 194 | void unmap_physical(void *virt_addr, size_t len); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 195 | |
| 196 | unsigned int cpuid(unsigned int op); |
| 197 | int print_intel_core_msrs(void); |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 198 | int print_mchbar(struct pci_dev *nb, struct pci_access *pacc); |
Tobias Diedrich | 3645e61 | 2010-11-27 14:44:19 +0000 | [diff] [blame] | 199 | int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 200 | int print_rcba(struct pci_dev *sb); |
Nico Huber | 09dcbf0 | 2013-04-01 15:08:04 +0200 | [diff] [blame] | 201 | int print_gpios(struct pci_dev *sb, int show_all, int show_diffs); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 202 | int print_epbar(struct pci_dev *nb); |
| 203 | int print_dmibar(struct pci_dev *nb); |
| 204 | int print_pciexbar(struct pci_dev *nb); |
Sven Schnelle | 4b7b320 | 2012-01-08 15:27:18 +0100 | [diff] [blame] | 205 | int print_ambs(struct pci_dev *nb, struct pci_access *pacc); |
Alexander Couzens | aa3dd5d | 2015-01-03 02:52:10 +0100 | [diff] [blame] | 206 | int print_spi(struct pci_dev *sb); |
Vladimir Serbinenko | 44bc11c | 2014-08-16 19:14:02 +0200 | [diff] [blame] | 207 | void ivybridge_dump_timings(void); |