blob: 3885257851781f15f60c51d4bd41196d34bf6434 [file] [log] [blame]
Aaron Durbinf6933a62012-10-30 09:09:39 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Aaron Durbinf6933a62012-10-30 09:09:39 -050014 */
15
16#include <string.h>
Kyösti Mälkki16455892014-04-28 23:41:06 +030017#include <bootmode.h>
Aaron Durbinf6933a62012-10-30 09:09:39 -050018#include <arch/io.h>
Aaron Durbinf6933a62012-10-30 09:09:39 -050019#include <device/device.h>
20#include <device/pci.h>
Aaron Durbinf6933a62012-10-30 09:09:39 -050021#include <southbridge/intel/lynxpoint/pch.h>
Aaron Durbin0160d762012-12-13 16:51:41 -060022#include <southbridge/intel/lynxpoint/gpio.h>
Aaron Durbinf6933a62012-10-30 09:09:39 -050023
24#ifndef __PRE_RAM__
25#include <boot/coreboot_tables.h>
Aaron Durbinf6933a62012-10-30 09:09:39 -050026
27#define GPIO_COUNT 6
Aaron Durbinf6933a62012-10-30 09:09:39 -050028
29void fill_lb_gpios(struct lb_gpios *gpios)
30{
31 device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
32 u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
33
34 if (!gpio_base)
35 return;
36
Aaron Durbin0160d762012-12-13 16:51:41 -060037 u32 gp_lvl = inl(gpio_base + GP_LVL);
38 u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
39 u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
Aaron Durbinf6933a62012-10-30 09:09:39 -050040
41 gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
42 gpios->count = GPIO_COUNT;
43
Aaron Durbin0160d762012-12-13 16:51:41 -060044 /* Write Protect: GPIO22 */
45 gpios->gpios[0].port = 0;
Aaron Durbinf6933a62012-10-30 09:09:39 -050046 gpios->gpios[0].polarity = ACTIVE_LOW;
Aaron Durbin0160d762012-12-13 16:51:41 -060047 gpios->gpios[0].value = (gp_lvl >> 22) & 1;
Aaron Durbinf6933a62012-10-30 09:09:39 -050048 strncpy((char *)gpios->gpios[0].name,"write protect",
49 GPIO_MAX_NAME_LENGTH);
50
Aaron Durbin0160d762012-12-13 16:51:41 -060051 /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */
52 gpios->gpios[1].port = 69;
53 gpios->gpios[1].polarity = ACTIVE_HIGH;
54 gpios->gpios[1].value = (gp_lvl3 >> (69-64)) & 1;
Aaron Durbinf6933a62012-10-30 09:09:39 -050055 strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
56
Aaron Durbin0160d762012-12-13 16:51:41 -060057 /* Developer: GPIO48 - BIOS_RESP - J8E4 (silkscreen: J8E3) */
58 gpios->gpios[2].port = 48;
Aaron Durbinf6933a62012-10-30 09:09:39 -050059 gpios->gpios[2].polarity = ACTIVE_LOW;
Aaron Durbin0160d762012-12-13 16:51:41 -060060 gpios->gpios[2].value = (gp_lvl2 >> (48-32)) & 1;
Aaron Durbinf6933a62012-10-30 09:09:39 -050061 strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
62
63 /* Hard code the lid switch GPIO to open. */
64 gpios->gpios[3].port = -1;
65 gpios->gpios[3].polarity = ACTIVE_HIGH;
66 gpios->gpios[3].value = 1;
67 strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
68
69 /* Power Button */
70 gpios->gpios[4].port = -1;
71 gpios->gpios[4].polarity = ACTIVE_HIGH;
72 gpios->gpios[4].value = 0;
73 strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
74
75 /* Did we load the VGA option ROM? */
76 gpios->gpios[5].port = -1;
77 gpios->gpios[5].polarity = ACTIVE_HIGH;
Kyösti Mälkkiab56b3b2013-11-28 16:44:51 +020078 gpios->gpios[5].value = gfx_get_init_done();
Aaron Durbinf6933a62012-10-30 09:09:39 -050079 strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
80}
81#endif
82
83int get_developer_mode_switch(void)
84{
85 device_t dev;
86#ifdef __PRE_RAM__
87 dev = PCI_DEV(0, 0x1f, 0);
88#else
89 dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
90#endif
91 u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
Aaron Durbin0160d762012-12-13 16:51:41 -060092 u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
Aaron Durbinf6933a62012-10-30 09:09:39 -050093
Aaron Durbin0160d762012-12-13 16:51:41 -060094 /*
95 * Developer: GPIO48, Connected to J8E4, however the silkscreen says
96 * J8E3. The jumper is active low.
97 */
98 return !((gp_lvl2 >> (48-32)) & 1);
Aaron Durbinf6933a62012-10-30 09:09:39 -050099}
100
101int get_recovery_mode_switch(void)
102{
103 device_t dev;
104#ifdef __PRE_RAM__
105 dev = PCI_DEV(0, 0x1f, 0);
106#else
107 dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
108#endif
109 u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
Aaron Durbin0160d762012-12-13 16:51:41 -0600110 u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
Aaron Durbinf6933a62012-10-30 09:09:39 -0500111
Aaron Durbin0160d762012-12-13 16:51:41 -0600112 /*
113 * Recovery: GPIO69, Connected to J8E3, however the silkscreen says
114 * J8E2. The jump is active high.
115 */
116 return (gp_lvl3 >> (69-64)) & 1;
Aaron Durbinf6933a62012-10-30 09:09:39 -0500117}
118
Aaron Durbin0df4de92013-03-01 17:38:59 -0600119int get_write_protect_state(void)
120{
121 return 0;
122}