Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2018 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <assert.h> |
| 17 | #include <chip.h> |
Lijian Zhao | 68890b9 | 2019-03-27 17:06:41 -0700 | [diff] [blame] | 18 | #include <cpu/x86/msr.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 19 | #include <console/console.h> |
| 20 | #include <fsp/util.h> |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 21 | #include <intelblocks/pmclib.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 22 | #include <soc/iomap.h> |
Lijian Zhao | 68890b9 | 2019-03-27 17:06:41 -0700 | [diff] [blame] | 23 | #include <soc/msr.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 24 | #include <soc/pci_devs.h> |
| 25 | #include <soc/romstage.h> |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 26 | #include <vendorcode/google/chromeos/chromeos.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 27 | |
| 28 | static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) |
| 29 | { |
| 30 | unsigned int i; |
| 31 | uint32_t mask = 0; |
Lijian Zhao | fe701ee | 2018-10-25 09:29:10 -0700 | [diff] [blame] | 32 | const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH); |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 33 | |
| 34 | /* Set IGD stolen size to 64MB. */ |
| 35 | m_cfg->IgdDvmt50PreAlloc = 2; |
| 36 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
| 37 | m_cfg->IedSize = CONFIG_IED_REGION_SIZE; |
| 38 | m_cfg->SaGv = config->SaGv; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 39 | if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 40 | m_cfg->UserBd = BOARD_TYPE_DESKTOP; |
| 41 | else |
| 42 | m_cfg->UserBd = BOARD_TYPE_ULT_ULX; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 43 | m_cfg->RMT = config->RMT; |
| 44 | |
| 45 | for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { |
| 46 | if (config->PcieRpEnable[i]) |
| 47 | mask |= (1 << i); |
| 48 | } |
| 49 | m_cfg->PcieRpEnableMask = mask; |
| 50 | m_cfg->PrmrrSize = config->PrmrrSize; |
| 51 | m_cfg->EnableC6Dram = config->enable_c6dram; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 52 | m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; |
Maulik V Vaghela | bfe4a59 | 2019-03-13 18:16:01 +0530 | [diff] [blame] | 53 | /* |
| 54 | * PcdDebugInterfaceFlags |
| 55 | * This config will allow coreboot to pass information to the FSP |
| 56 | * regarding which debug interface is being used. |
| 57 | * Debug Interfaces: |
| 58 | * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub |
| 59 | * BIT2 - Not used. |
| 60 | */ |
| 61 | m_cfg->PcdDebugInterfaceFlags = |
| 62 | CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; |
| 63 | |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 64 | /* Disable Vmx if Vt-d is already disabled */ |
| 65 | if (config->VtdDisable) |
| 66 | m_cfg->VmxEnable = 0; |
| 67 | else |
| 68 | m_cfg->VmxEnable = config->VmxEnable; |
Subrata Banik | cf32fd1 | 2018-12-19 18:02:17 +0530 | [diff] [blame] | 69 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 70 | #if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) |
Subrata Banik | 41dad28 | 2019-04-12 14:39:42 +0530 | [diff] [blame] | 71 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
| 72 | m_cfg->SkipMpInit = 0; |
| 73 | else |
| 74 | m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 75 | #endif |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 76 | |
Lijian Zhao | 68890b9 | 2019-03-27 17:06:41 -0700 | [diff] [blame] | 77 | /* Set CpuRatio to match existing MSR value */ |
| 78 | msr_t flex_ratio; |
| 79 | flex_ratio = rdmsr(MSR_FLEX_RATIO); |
| 80 | m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 81 | |
Lijian Zhao | fe701ee | 2018-10-25 09:29:10 -0700 | [diff] [blame] | 82 | /* If ISH is enabled, enable ISH elements */ |
| 83 | if (!dev) |
| 84 | m_cfg->PchIshEnable = 0; |
| 85 | else |
| 86 | m_cfg->PchIshEnable = dev->enabled; |
Lijian Zhao | 3ef7449 | 2018-12-06 17:29:55 -0800 | [diff] [blame] | 87 | |
| 88 | /* If HDA is enabled, enable HDA elements */ |
| 89 | dev = dev_find_slot(0, PCH_DEVFN_HDA); |
| 90 | if (!dev) |
| 91 | m_cfg->PchHdaEnable = 0; |
| 92 | else |
| 93 | m_cfg->PchHdaEnable = dev->enabled; |
| 94 | |
V Sowmya | 0bc3e3d | 2019-01-07 13:11:29 +0530 | [diff] [blame] | 95 | /* Enable IPU only if the device is enabled */ |
| 96 | m_cfg->SaIpuEnable = 0; |
| 97 | dev = pcidev_path_on_root(SA_DEVFN_IPU); |
| 98 | if (dev) |
| 99 | m_cfg->SaIpuEnable = dev->enabled; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 103 | { |
| 104 | const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); |
Duncan Laurie | 25b387a | 2018-11-08 15:48:14 -0700 | [diff] [blame] | 105 | const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS); |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 106 | assert(dev != NULL); |
| 107 | const config_t *config = dev->chip_info; |
| 108 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
| 109 | |
| 110 | soc_memory_init_params(m_cfg, config); |
| 111 | |
| 112 | /* Enable SMBus controller based on config */ |
Duncan Laurie | 25b387a | 2018-11-08 15:48:14 -0700 | [diff] [blame] | 113 | if (!smbus) |
| 114 | m_cfg->SmbusEnable = 0; |
| 115 | else |
| 116 | m_cfg->SmbusEnable = smbus->enabled; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 117 | /* Set debug probe type */ |
| 118 | m_cfg->PlatformDebugConsent = config->DebugConsent; |
| 119 | |
| 120 | mainboard_memory_init_params(mupd); |
| 121 | } |
| 122 | |
| 123 | __weak void mainboard_memory_init_params(FSPM_UPD *mupd) |
| 124 | { |
| 125 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 126 | } |