Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2006 Tyan |
| 5 | * Copyright (C) 2006 AMD |
| 6 | * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD. |
| 7 | * |
| 8 | * Copyright (C) 2007 University of Mannheim |
| 9 | * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim |
| 10 | * Copyright (C) 2009 University of Heidelberg |
| 11 | * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License as published by |
| 15 | * the Free Software Foundation; either version 2 of the License, or |
| 16 | * (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 26 | */ |
| 27 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 28 | #define RAMINIT_SYSINFO 1 |
| 29 | |
| 30 | #define K8_ALLOCATE_IO_RANGE 1 |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 31 | |
| 32 | #define QRANK_DIMM_SUPPORT 1 |
| 33 | |
| 34 | #if CONFIG_LOGICAL_CPUS==1 |
| 35 | #define SET_NB_CFG_54 1 |
| 36 | #endif |
| 37 | |
| 38 | //used by init_cpus and fidvid |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 39 | #define SET_FIDVID 1 |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 40 | //if we want to wait for core1 done before DQS training, set it to 0 |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 41 | #define SET_FIDVID_CORE0_ONLY 1 |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 42 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 43 | #if CONFIG_K8_REV_F_SUPPORT == 1 |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 44 | #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 |
| 45 | #endif |
| 46 | |
| 47 | #define DBGP_DEFAULT 7 |
| 48 | |
| 49 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 50 | #include <string.h> |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 51 | #include <device/pci_def.h> |
| 52 | #include <device/pci_ids.h> |
| 53 | #include <arch/io.h> |
| 54 | #include <device/pnp_def.h> |
| 55 | #include <arch/romcc_io.h> |
| 56 | #include <cpu/x86/lapic.h> |
| 57 | #include "option_table.h" |
| 58 | #include "pc80/mc146818rtc_early.c" |
| 59 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 60 | #include "pc80/serial.c" |
Stefan Reinauer | 5a1f597 | 2010-03-31 14:34:40 +0000 | [diff] [blame] | 61 | #include "console/console.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 62 | #include "lib/ramtest.c" |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 63 | |
| 64 | #include <cpu/amd/model_fxx_rev.h> |
| 65 | |
| 66 | #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" |
| 67 | #include "northbridge/amd/amdk8/raminit.h" |
| 68 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 69 | #include "lib/delay.c" |
| 70 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 71 | #include "cpu/x86/lapic/boot_cpu.c" |
| 72 | #include "northbridge/amd/amdk8/reset_test.c" |
| 73 | |
| 74 | #include "superio/serverengines/pilot/pilot_early_serial.c" |
| 75 | #include "superio/serverengines/pilot/pilot_early_init.c" |
| 76 | #include "superio/nsc/pc87417/pc87417_early_serial.c" |
| 77 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 78 | #include "cpu/x86/bist.h" |
| 79 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 80 | #include "northbridge/amd/amdk8/debug.c" |
| 81 | |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 82 | #include "cpu/x86/mtrr/earlymtrr.c" |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 83 | |
| 84 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 85 | |
| 86 | #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) |
| 87 | #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) |
| 88 | |
| 89 | #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" |
| 90 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 91 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 92 | { |
| 93 | } |
| 94 | |
| 95 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 96 | { |
| 97 | #define SMBUS_SWITCH1 0x70 |
| 98 | #define SMBUS_SWITCH2 0x72 |
| 99 | unsigned device = (ctrl->channel0[0]) >> 8; |
| 100 | smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); |
| 101 | smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); |
| 102 | } |
| 103 | |
| 104 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 105 | { |
| 106 | return smbus_read_byte(device, address); |
| 107 | } |
| 108 | |
| 109 | #include "northbridge/amd/amdk8/amdk8_f.h" |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 110 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Stefan Reinauer | 23836e2 | 2010-04-15 12:39:29 +0000 | [diff] [blame^] | 111 | #include "northbridge/amd/amdk8/coherent_ht.c" |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 112 | #include "northbridge/amd/amdk8/raminit_f.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 113 | #include "lib/generic_sdram.c" |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 114 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 115 | #include "cpu/amd/dualcore/dualcore.c" |
| 116 | |
| 117 | //first node |
| 118 | #define DIMM0 0x50 |
| 119 | #define DIMM1 0x51 |
| 120 | #define DIMM2 0x52 |
| 121 | #define DIMM3 0x53 |
| 122 | //second node |
| 123 | #define DIMM4 0x54 |
| 124 | #define DIMM5 0x55 |
| 125 | #define DIMM6 0x56 |
| 126 | #define DIMM7 0x57 |
| 127 | |
Stefan Reinauer | 853263b | 2010-04-09 10:43:49 +0000 | [diff] [blame] | 128 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 129 | |
| 130 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 131 | |
| 132 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 133 | |
| 134 | #include "cpu/amd/model_fxx/fidvid.c" |
| 135 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 136 | #include "northbridge/amd/amdk8/early_ht.c" |
| 137 | |
| 138 | #if 0 |
| 139 | #include "ipmi.c" |
| 140 | |
| 141 | static void setup_early_ipmi_serial() |
| 142 | { |
| 143 | unsigned char result; |
| 144 | char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05}; |
| 145 | char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f}; |
| 146 | char serial_mux1[]={0x0c<<2,0x12,0x04,0x06}; |
| 147 | char serial_mux2[]={0x0c<<2,0x12,0x04,0x03}; |
| 148 | char serial_mux3[]={0x0c<<2,0x12,0x04,0x07}; |
| 149 | |
| 150 | // earlydbg(0x0d); |
| 151 | //set channel access system only |
| 152 | ipmi_request(5,channel_access); |
| 153 | // earlydbg(result); |
| 154 | /* |
| 155 | //Set serial/modem config |
| 156 | result=ipmi_request(6,serialmodem_conf); |
| 157 | earlydbg(result); |
| 158 | |
| 159 | //Set serial mux 1 |
| 160 | result=ipmi_request(4,serial_mux1); |
| 161 | earlydbg(result); |
| 162 | |
| 163 | //Set serial mux 2 |
| 164 | result=ipmi_request(4,serial_mux2); |
| 165 | earlydbg(result); |
| 166 | |
| 167 | //Set serial mux 3 |
| 168 | result=ipmi_request(4,serial_mux3); |
| 169 | earlydbg(result); |
| 170 | */ |
| 171 | // earlydbg(0x0e); |
| 172 | |
| 173 | } |
| 174 | #endif |
| 175 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 176 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 177 | { |
| 178 | static const uint16_t spd_addr[] = { |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 179 | // first node |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 180 | DIMM0, DIMM2, 0, 0, |
| 181 | DIMM1, DIMM3, 0, 0, |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 182 | |
| 183 | // second node |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 184 | DIMM4, DIMM6, 0, 0, |
| 185 | DIMM5, DIMM7, 0, 0, |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 186 | }; |
| 187 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 188 | struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 189 | |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 190 | int needs_reset; |
| 191 | unsigned bsp_apicid = 0; |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 192 | |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 193 | if (!cpu_init_detectedx && boot_cpu()) { |
| 194 | /* Nothing special needs to be done to find bus 0 */ |
| 195 | /* Allow the HT devices to be found */ |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 196 | |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 197 | enumerate_ht_chain(); |
| 198 | bcm5785_enable_rom(); |
| 199 | bcm5785_enable_lpc(); |
| 200 | //enable RTC |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 201 | pc87417_enable_dev(RTC_DEV); |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 202 | } |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 203 | |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 204 | if (bist == 0) { |
| 205 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 206 | } |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 207 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 208 | pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 209 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 210 | uart_init(); |
| 211 | |
| 212 | /* Halt if there was a built in self test failure */ |
| 213 | report_bist_failure(bist); |
| 214 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 215 | console_init(); |
| 216 | // setup_early_ipmi_serial(); |
| 217 | pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 218 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 219 | |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 220 | print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 221 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 222 | #if CONFIG_MEM_TRAIN_SEQ == 1 |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 223 | set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram |
| 224 | #endif |
| 225 | setup_coherent_ht_domain(); |
| 226 | |
| 227 | wait_all_core0_started(); |
| 228 | #if CONFIG_LOGICAL_CPUS==1 |
| 229 | // It is said that we should start core1 after all core0 launched |
| 230 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
| 231 | * So here need to make sure last core0 is started, esp for two way system, |
| 232 | * (there may be apic id conflicts in that case) |
| 233 | */ |
| 234 | start_other_cores(); |
| 235 | wait_all_other_cores_started(bsp_apicid); |
| 236 | #endif |
| 237 | |
| 238 | /* it will set up chains and store link pair for optimization later */ |
| 239 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 240 | bcm5785_early_setup(); |
| 241 | |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 242 | #if SET_FIDVID == 1 |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 243 | { |
| 244 | msr_t msr; |
| 245 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 246 | print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 247 | } |
| 248 | enable_fid_change(); |
| 249 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 250 | init_fidvid_bsp(bsp_apicid); |
| 251 | // show final fid and vid |
| 252 | { |
| 253 | msr_t msr; |
| 254 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 255 | print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 256 | } |
| 257 | #endif |
| 258 | |
| 259 | needs_reset = optimize_link_coherent_ht(); |
| 260 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 261 | |
| 262 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 263 | if (needs_reset) { |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 264 | print_info("ht reset -\n"); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 265 | soft_reset(); |
| 266 | } |
| 267 | |
| 268 | allow_all_aps_stop(bsp_apicid); |
| 269 | |
| 270 | //It's the time to set ctrl in sysinfo now; |
| 271 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 272 | enable_smbus(); |
| 273 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 274 | //do we need apci timer, tsc...., only debug need it for better output |
| 275 | /* all ap stopped? */ |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 276 | // init_timer(); // Need to use TMICT to synconize FID/VID |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 277 | |
| 278 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 279 | |
| 280 | post_cache_as_ram(); |
| 281 | |
| 282 | } |
| 283 | |