Peter Stuge | dad1e30 | 2008-11-22 17:13:36 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of msrtool. |
| 3 | * |
| 4 | * Copyright (c) 2008 Peter Stuge <peter@stuge.se> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include "msrtool.h" |
| 21 | |
| 22 | int geodelx_probe(const struct targetdef *target) { |
| 23 | struct cpuid_t *id = cpuid(); |
Peter Stuge | 46c920e | 2009-11-25 02:25:37 +0000 | [diff] [blame] | 24 | return 5 == id->family && 10 == id->model; |
Peter Stuge | dad1e30 | 2008-11-22 17:13:36 +0000 | [diff] [blame] | 25 | } |
| 26 | |
| 27 | const struct msrdef geodelx_msrs[] = { |
| 28 | { 0x4c00000f, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_DELAY_CONTROLS", "GLCP I/O Delay Controls", { |
| 29 | { 63, 1, "EN", "Enable", PRESENT_DEC, { |
| 30 | { MSR1(0), "Use default values" }, |
| 31 | { MSR1(1), "Use value in bits [62:0]" }, |
| 32 | { BITVAL_EOT } |
| 33 | }}, |
| 34 | { 62, 1, "B_DQ", "Buffer Control for DQ DQS DQM TLA drive", PRESENT_DEC, { |
| 35 | { MSR1(1), "Half power" }, |
| 36 | { MSR1(0), "Quarter power" }, |
| 37 | { BITVAL_EOT } |
| 38 | }}, |
| 39 | { 61, 1, "B_CMD", "Buffer Control for RAS CAS CKE CS WE drive", PRESENT_DEC, { |
| 40 | { MSR1(1), "Half power" }, |
| 41 | { MSR1(0), "Quarter power" }, |
| 42 | { BITVAL_EOT } |
| 43 | }}, |
| 44 | { 60, 1, "B_MA", "Buffer Control for MA BA drive", PRESENT_DEC, { |
| 45 | { MSR1(0), "Half power" }, |
| 46 | { MSR1(1), "Full power" }, |
| 47 | { BITVAL_EOT } |
| 48 | }}, |
| 49 | { 59, 1, "SDCLK_SET", "SDCLK Setup", PRESENT_DEC, { |
| 50 | { MSR1(0), "Full SDCLK setup" }, |
| 51 | { MSR1(1), "Half SDCLK setup for control signals" }, |
| 52 | { BITVAL_EOT } |
| 53 | }}, |
| 54 | { 58, 3, "DDR_RLE", "DDR read latch enable position", PRESENT_DEC, NOBITS }, |
| 55 | { 55, 1, "SDCLK_DIS", "SDCLK disable [1,3,5]", PRESENT_DEC, { |
| 56 | { MSR1(0), "All SDCLK output" }, |
| 57 | { MSR1(1), "SDCLK[0,2,4] output only" }, |
| 58 | { BITVAL_EOT } |
| 59 | }}, |
| 60 | { 54, 3, "TLA1_OA", "TLA hint pin output adjust", PRESENT_DEC, NOBITS }, |
| 61 | { 51, 2, "D_TLA1", "Output delay for TLA1", PRESENT_DEC, NOBITS }, |
| 62 | { 49, 2, "D_TLA0", "Output delay for TLA0", PRESENT_DEC, NOBITS }, |
| 63 | { 47, 2, "D_DQ_E", "Output delay for DQ DQM - even byte lanes", PRESENT_DEC, NOBITS }, |
| 64 | { 45, 2, "D_DQ_O", "Output delay for DQ DQM - odd byte lanes", PRESENT_DEC, NOBITS }, |
| 65 | { 43, 2, RESERVED}, |
| 66 | { 41, 2, "D_SDCLK", "Output delay for SDCLK", PRESENT_DEC, NOBITS }, |
| 67 | { 39, 2, "D_CMD_O", "Output delay for CKE CS RAS CAS WE - odd bits", PRESENT_DEC, NOBITS }, |
| 68 | { 37, 2, "D_CMD_E", "Output delay for CKE CS RAS CAS WE - even bits", PRESENT_DEC, NOBITS }, |
| 69 | { 35, 2, "D_MA_O", "Output delay for BA MA - odd bits", PRESENT_DEC, NOBITS }, |
| 70 | { 33, 2, "D_MA_E", "Output delay for BA MA - even bits", PRESENT_DEC, NOBITS }, |
| 71 | { 31, 2, "D_PCI_O", "Output delay for pci_ad IRQ13 SUSPA# INTA# - odd bits", PRESENT_DEC, NOBITS }, |
| 72 | { 29, 2, "D_PCI_E", "Output delay for pci_ad IRQ13 SUSPA# INTA# - even bits", PRESENT_DEC, NOBITS }, |
| 73 | { 27, 2, "D_DOTCLK", "Output delay for DOTCLK", PRESENT_DEC, NOBITS }, |
| 74 | { 25, 2, "D_DRGB_O", "Output delay for DRGB[31:0] - odd bits", PRESENT_DEC, NOBITS }, |
| 75 | { 23, 2, "D_DRGB_E", "Output delay for DRGB[31:0] HSYNC VSYNC DISPEN VDDEN LDE_MOD - even bits", PRESENT_DEC, NOBITS }, |
| 76 | { 21, 2, "D_PCI_IN", "Input delay for pci_ad CBE# PAR STOP# FRAME# IRDY# TRDY# DEVSEL# REQ# GNT# CIS", PRESENT_DEC, NOBITS }, |
| 77 | { 19, 2, "D_TDBGI", "Input delay for TDBGI", PRESENT_DEC, NOBITS }, |
| 78 | { 17, 2, "D_VIP", "Input delay for VID[15:0] VIP_HSYNC VIP_VSYNC", PRESENT_DEC, NOBITS }, |
| 79 | { 15, 2, "D_VIPCLK", "Input delay for VIPCLK", PRESENT_DEC, NOBITS }, |
| 80 | { 13, 1, "H_SDCLK", "Half SDCLK hold select (for cmd addr)", PRESENT_DEC, { |
| 81 | { MSR1(1), "Half SDCLK setup for MA and BA" }, |
| 82 | { MSR1(0), "Full SDCLK setup" }, |
| 83 | { BITVAL_EOT } |
| 84 | }}, |
| 85 | { 12, 2, "PLL_FD_DEL", "PLL Feedback Delay", PRESENT_BIN, { |
| 86 | { MSR1(0), "No feedback delay" }, |
| 87 | { MSR1(1), "~350 ps" }, |
| 88 | { MSR1(2), "~700 ps" }, |
| 89 | { MSR1(3), "~1100 ps (Max feedback delay)" }, |
| 90 | { BITVAL_EOT } |
| 91 | }}, |
| 92 | { 10, 5, RESERVED }, |
| 93 | { 5, 1, "DLL_OV", "DLL Override (to DLL)", PRESENT_DEC, NOBITS }, |
| 94 | { 4, 5, "DLL_OVS/RSDA", "DLL Override Setting or Read Strobe Delay Adjust", PRESENT_DEC, NOBITS }, |
| 95 | { BITS_EOT } |
| 96 | }}, |
Peter Stuge | b198a47 | 2009-11-21 06:02:48 +0000 | [diff] [blame] | 97 | { 0x4c000014, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_SYS_RSTPLL", "GLCP System Reset and PLL Control", { |
| 98 | { 63, 20, RESERVED }, |
| 99 | { 43, 5, "GLIUMULT", "GLIU Multiplier", PRESENT_DEC, NOBITS }, |
| 100 | { 38, 1, "GLIUDIV", "GLIU Divide", PRESENT_DEC, { |
| 101 | { MSR1(0), "Do not predivide input" }, |
| 102 | { MSR1(1), "Divide by 2" }, |
| 103 | { BITVAL_EOT } |
| 104 | }}, |
| 105 | { 37, 5, "COREMULT", "CPU Core Multiplier", PRESENT_DEC, NOBITS }, |
| 106 | { 32, 1, "COREDIV", "CPU Core Divide", PRESENT_DEC, { |
| 107 | { MSR1(0), "Do not predivide input" }, |
| 108 | { MSR1(1), "Divide by 2" }, |
| 109 | { BITVAL_EOT } |
| 110 | }}, |
| 111 | { 31, 6, "SWFLAGS", "Flags", PRESENT_BIN, NOBITS }, |
| 112 | { 25, 1, "GLIULOCK", "GLIU PLL Lock", PRESENT_DEC, { |
| 113 | { MSR1(1), "PLL locked" }, |
| 114 | { MSR1(0), "PLL is not locked" }, |
| 115 | { BITVAL_EOT } |
| 116 | }}, |
| 117 | { 24, 1, "CORELOCK", "CPU Core PLL Lock", PRESENT_DEC, { |
| 118 | { MSR1(1), "PLL locked" }, |
| 119 | { MSR1(0), "PLL is not locked" }, |
| 120 | { BITVAL_EOT } |
| 121 | }}, |
| 122 | { 23, 8, "HOLD_COUNT", "Hold Count, divided by 16", PRESENT_DEC, NOBITS }, |
| 123 | { 15, 1, RESERVED }, |
| 124 | { 14, 1, "GLIUPD", "GLIU PLL Power Down mode", PRESENT_DEC, NOBITS }, |
| 125 | { 13, 1, "COREPD", "CPU Core PLL Power Down mode", PRESENT_DEC, NOBITS }, |
| 126 | { 12, 1, "GLIUBYPASS", "GLIU PLL Bypass", PRESENT_DEC, { |
| 127 | { MSR1(1), "DOTREF input directly drives the GLIU clock spines" }, |
| 128 | { MSR1(0), "DOTPLL drives the GLIU clock" }, |
| 129 | { BITVAL_EOT } |
| 130 | }}, |
| 131 | { 11, 1, "COREBYPASS", "CPU Core PLL Bypass", PRESENT_DEC, { |
| 132 | { MSR1(1), "DOTREF input directly drives the CPU Core clock" }, |
| 133 | { MSR1(0), "DOTPLL drives the CPU Core clock" }, |
| 134 | { BITVAL_EOT } |
| 135 | }}, |
| 136 | { 10, 1, "LPFEN", "Loop Filter", PRESENT_DEC, { |
| 137 | { MSR1(1), "Enabled" }, |
| 138 | { MSR1(0), "Disabled" }, |
| 139 | { BITVAL_EOT } |
| 140 | }}, |
| 141 | { 9, 1, "VA_SEMI_SYNC_MODE", "CPU-GLIU Sync Mode", PRESENT_DEC, { |
| 142 | { MSR1(1), "CPU does not use GLIU FIFO" }, |
| 143 | { MSR1(0), "The GLIU FIFO is used by the CPU" }, |
| 144 | { BITVAL_EOT } |
| 145 | }}, |
| 146 | { 8, 1, "PCI_SEMI_SYNC_MODE", "PCI-GLIU Sync Mode", PRESENT_DEC, { |
| 147 | { MSR1(1), "PCI does not use mb_func_clk and pci_func_clk falling edges" }, |
| 148 | { MSR1(0), "Falling edges on mb_func_clk and pci_func_clk are used by PCI" }, |
| 149 | { BITVAL_EOT } |
| 150 | }}, |
| 151 | { 7, 1, "BOOTSTRAP_PW1", "PW1 bootstrap", PRESENT_DEC, { |
| 152 | { MSR1(1), "66MHz PCI clock" }, |
| 153 | { MSR1(0), "33MHz PCI clock" }, |
| 154 | { BITVAL_EOT } |
| 155 | }}, |
| 156 | { 6, 1, "BOOTSTRAP_IRQ13", "IRQ13 bootstrap", PRESENT_DEC, { |
| 157 | { MSR1(1), "Stall-on-reset debug feature enabled" }, |
| 158 | { MSR1(0), "No stall" }, |
| 159 | { BITVAL_EOT } |
| 160 | }}, |
| 161 | { 5, 5, "BOOTSTRAPS", "CPU/GLIU frequency select", PRESENT_BIN, NOBITS }, |
| 162 | { 0, 1, "CHIP_RESET", "Chip Reset", PRESENT_DEC, NOBITS }, |
| 163 | { BITS_EOT } |
| 164 | }}, |
Peter Stuge | dad1e30 | 2008-11-22 17:13:36 +0000 | [diff] [blame] | 165 | /* |
| 166 | { 0, MSRTYPE_RDONLY, MSR2(0, 0), "TEMPLATE", "Template MSR", { |
| 167 | { 63, 64, RESERVED }, |
| 168 | { BITS_EOT } |
| 169 | }}, |
| 170 | */ |
| 171 | { MSR_EOT } |
| 172 | }; |