blob: e0b8b7d5626f1500dec2ac27515b2d78b8b8f63d [file] [log] [blame]
Chris Wang5547c372017-10-05 21:57:16 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2017 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <baseboard/gpio.h>
17#include <baseboard/variants.h>
18#include <commonlib/helpers.h>
19
20/* Pad configuration in ramstage */
21/* Leave eSPI pins untouched from default settings */
22static const struct pad_config gpio_table[] = {
Chris Wangcb259742017-10-26 18:40:11 +080023 /* A0 : RCIN# ==> NC(TP763) */
Chris Wang5547c372017-10-05 21:57:16 +080024 PAD_CFG_NC(GPP_A0),
25 /* A1 : ESPI_IO0 */
26 /* A2 : ESPI_IO1 */
27 /* A3 : ESPI_IO2 */
28 /* A4 : ESPI_IO3 */
29 /* A5 : ESPI_CS# */
Chris Wangcb259742017-10-26 18:40:11 +080030 /* A6 : SERIRQ ==> NC(TP764) */
Chris Wang5547c372017-10-05 21:57:16 +080031 PAD_CFG_NC(GPP_A6),
Chris Wangcb259742017-10-26 18:40:11 +080032 /* A7 : PIRQA# ==> NC(TP703) */
Chris Wang5547c372017-10-05 21:57:16 +080033 PAD_CFG_NC(GPP_A7),
Chris Wangcb259742017-10-26 18:40:11 +080034 /* A8 : CLKRUN# ==> NC(TP758)) */
Chris Wang5547c372017-10-05 21:57:16 +080035 PAD_CFG_NC(GPP_A8),
36 /* A9 : ESPI_CLK */
37 /* A10 : CLKOUT_LPC1 ==> NC */
38 PAD_CFG_NC(GPP_A10),
Chris Wangcb259742017-10-26 18:40:11 +080039 /* A11 : PME# ==> NC(TP726) */
Chris Wang5547c372017-10-05 21:57:16 +080040 PAD_CFG_NC(GPP_A11),
41 /* A12 : BM_BUSY# ==> NC */
42 PAD_CFG_NC(GPP_A12),
43 /* A13 : SUSWARN# ==> SUSWARN_L */
44 PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
45 /* A14 : ESPI_RESET# */
46 /* A15 : SUSACK# ==> SUSACK_L */
47 PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +080048 /* A16 : SD_1P8_SEL ==> CPU1_P1.8V_SEL */
Chris Wang5547c372017-10-05 21:57:16 +080049 PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +080050 /* A17 : SD_PWR_EN# ==> CPU1_SDCARD_PWREN_L */
Chris Wang5547c372017-10-05 21:57:16 +080051 PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
52 /* A18 : ISH_GP0 ==> NC */
53 PAD_CFG_NC(GPP_A18),
54 /* A19 : ISH_GP1 ==> NC */
55 PAD_CFG_NC(GPP_A19),
Chris Wangcb259742017-10-26 18:40:11 +080056 /* A20 : ISH_GP2 ==> NC */
57 PAD_CFG_NC(GPP_A20),
58 /* A21 : ISH_GP3 ==> CHP1_DIG_PDCT_L */
59 PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST),
60 /* A22 : ISH_GP4 ==> CHP1_DIG_IRQ_L */
61 PAD_CFG_GPI_APIC(GPP_A22, NONE, PLTRST),
62 /* A23 : ISH_GP5 ==> CHP1_SPK_PA_EN */
63 PAD_CFG_GPO(GPP_A23, 1, DEEP),
Chris Wang5547c372017-10-05 21:57:16 +080064
Seunghwan Kimdf2ae962018-02-01 14:33:04 +090065 /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */
66 PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT),
Chris Wangcb259742017-10-26 18:40:11 +080067 /* B1 : CORE_VID1 ==> NC(TP722) */
Chris Wang5547c372017-10-05 21:57:16 +080068 PAD_CFG_NC(GPP_B1),
69 /* B2 : VRALERT# ==> NC */
70 PAD_CFG_NC(GPP_B2),
Chris Wangcb259742017-10-26 18:40:11 +080071 /* B3 : CPU_GP2 ==> CHP3_TP_INT_L */
72 PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
Chris Wang5547c372017-10-05 21:57:16 +080073 /* B4 : CPU_GP3 ==> NC */
74 PAD_CFG_NC(GPP_B4),
Chris Wangcb259742017-10-26 18:40:11 +080075 /* B5 : SRCCLKREQ0# ==> CHP3_TP_INT_L - for wake event */
76 PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT),
77 /* B6 : SRCCLKREQ1# ==> CHP3_WLAN_CLKREQ_L */
Chris Wang5547c372017-10-05 21:57:16 +080078 PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
79 /* B7 : SRCCLKREQ2# ==> NC */
80 PAD_CFG_NC(GPP_B7),
Chris Wangcb259742017-10-26 18:40:11 +080081 /* B8 : SRCCLKREQ3# ==> CHP3_WLAN_PE_RST */
82 PAD_CFG_GPO(GPP_B8, 0, DEEP),
Chris Wang5547c372017-10-05 21:57:16 +080083 /* B9 : SRCCLKREQ4# ==> NC */
84 PAD_CFG_NC(GPP_B9),
85 /* B10 : SRCCLKREQ5# ==> NC */
86 PAD_CFG_NC(GPP_B10),
87 /* B11 : EXT_PWR_GATE# ==> NC */
88 PAD_CFG_NC(GPP_B11),
Chris Wangcb259742017-10-26 18:40:11 +080089 /* B12 : SLP_S0# ==> CHP3_SLPS0_L_ORG */
Chris Wang5547c372017-10-05 21:57:16 +080090 PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +080091 /* B13 : PLTRST# ==> PLT3_RST_L */
Chris Wang5547c372017-10-05 21:57:16 +080092 PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
93 /* B14 : SPKR ==> NC */
94 PAD_CFG_NC(GPP_B14),
Chris Wang5547c372017-10-05 21:57:16 +080095 /* B15 : GSPI0_CS# ==> NC */
96 PAD_CFG_NC(GPP_B15),
97 /* B16 : GSPI0_CLK ==> NC */
98 PAD_CFG_NC(GPP_B16),
99 /* B17 : GSPI0_MISO ==> NC */
100 PAD_CFG_NC(GPP_B17),
101 /* B18 : GSPI0_MOSI ==> NC */
102 PAD_CFG_NC(GPP_B18),
Chris Wangcb259742017-10-26 18:40:11 +0800103 /* B19 : GSPI1_CS# ==> CHP3_PEN_EJECT - for notification */
Furquan Shaikhbb1e5392018-01-11 20:29:38 -0800104 PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP),
Chris Wang5547c372017-10-05 21:57:16 +0800105 /* B20 : GSPI1_CLK ==> NC */
106 PAD_CFG_NC(GPP_B20),
Chris Wangcb259742017-10-26 18:40:11 +0800107 /* B21 : GSPI1_MISO ==> CHP3_PEN_EJECT - for wake event */
108 PAD_CFG_GPI_ACPI_SCI(GPP_B21, NONE, DEEP, NONE),
Chris Wang5547c372017-10-05 21:57:16 +0800109 /* B22 : GSPI1_MOSI ==> NC */
110 PAD_CFG_NC(GPP_B22),
111 /* B23 : SM1ALERT# ==> NC */
112 PAD_CFG_NC(GPP_B23),
113
Chris Wangcb259742017-10-26 18:40:11 +0800114 /* C0 : SMBCLK ==> CHP3_SMBCLK */
115 PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
116 /* C1 : SMBDATA ==> CHP3_SMBDATA */
117 PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
Chris Wang5547c372017-10-05 21:57:16 +0800118 /* C2 : SMBALERT# ==> NC */
119 PAD_CFG_NC(GPP_C2),
120 /* C3 : SML0CLK ==> NC */
121 PAD_CFG_NC(GPP_C3),
122 /* C4 : SML0DATA ==> NC */
123 PAD_CFG_NC(GPP_C4),
124 /* C5 : SML0ALERT# ==> NC */
125 PAD_CFG_NC(GPP_C5),
Chris Wangcb259742017-10-26 18:40:11 +0800126 /* C6 : SM1CLK ==> CPU3_EC_IN_RW */
Chris Wang5547c372017-10-05 21:57:16 +0800127 PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),
128 /* C7 : SM1DATA ==> NC */
129 PAD_CFG_NC(GPP_C7),
Furquan Shaikh8a1f0952018-01-24 13:14:33 -0800130 /* C8 : UART0_RXD ==> CHP3_P3.3V_DX_WFCAM_EN */
131 PAD_CFG_GPO(GPP_C8, 0, DEEP),
Chris Wangcb259742017-10-26 18:40:11 +0800132 /* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */
Seunghwan Kim533ea7a2017-12-28 10:40:35 +0900133 PAD_CFG_GPO(GPP_C9, 0, DEEP),
Chris Wangcb259742017-10-26 18:40:11 +0800134 /* C10 : UART0_RTS# ==> CHP3_CAM_PMIC_RST_L */
Chris Wang5547c372017-10-05 21:57:16 +0800135 PAD_CFG_GPO(GPP_C10, 1, DEEP),
Furquan Shaikh8a1f0952018-01-24 13:14:33 -0800136 /* C11 : UART0_CTS# ==> CHP3_P3.3V_DX_UFCAM_EN */
Chris Wang5547c372017-10-05 21:57:16 +0800137 PAD_CFG_GPO(GPP_C11, 1, DEEP),
138 /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
139 PAD_CFG_GPI(GPP_C12, NONE, DEEP),
140 /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */
141 PAD_CFG_GPI(GPP_C13, NONE, DEEP),
142 /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */
143 PAD_CFG_GPI(GPP_C14, NONE, DEEP),
144 /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */
145 PAD_CFG_GPI(GPP_C15, NONE, DEEP),
Chris Wangcb259742017-10-26 18:40:11 +0800146 /* C16 : I2C0_SDA ==> CHP3_I2C0_TSP_SDA */
Chris Wang5547c372017-10-05 21:57:16 +0800147 PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800148 /* C17 : I2C0_SCL ==> CHP3_I2C0_TSP_SCL */
Chris Wang5547c372017-10-05 21:57:16 +0800149 PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
Chris Wang5547c372017-10-05 21:57:16 +0800150 /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
151 PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
152 /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
153 PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800154 /* C20 : UART2_RXD ==> CHP3_RX_SERVO_TX_UART */
Chris Wang5547c372017-10-05 21:57:16 +0800155 PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800156 /* C21 : UART2_TXD ==> CHP3_TX_SERVO_RX_UART */
Chris Wang5547c372017-10-05 21:57:16 +0800157 PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800158 /* C22 : UART2_RTS# ==> CHP3_P3.3V_DX_TSP_EN */
Chris Wang5547c372017-10-05 21:57:16 +0800159 PAD_CFG_GPO(GPP_C22, 0, DEEP),
Chris Wangcb259742017-10-26 18:40:11 +0800160 /* C23 : UART2_CTS# ==> CHP3_PCH_WP*/
Chris Wang5547c372017-10-05 21:57:16 +0800161 PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
162
163 /* D0 : SPI1_CS# ==> NC */
164 PAD_CFG_NC(GPP_D0),
165 /* D1 : SPI1_CLK ==> NC */
166 PAD_CFG_NC(GPP_D1),
167 /* D2 : SPI1_MISO ==> NC */
168 PAD_CFG_NC(GPP_D2),
169 /* D3 : SPI1_MOSI ==> NC */
170 PAD_CFG_NC(GPP_D3),
Chris Wangcb259742017-10-26 18:40:11 +0800171 /* D4 : FASHTRIG ==> CHP1_VDD_CAM_CORE_EN */
Chris Wang5547c372017-10-05 21:57:16 +0800172 PAD_CFG_NC(GPP_D4),
Chris Wangcb259742017-10-26 18:40:11 +0800173 /* D5 : ISH_I2C0_SDA ==> CHP1_I2C_ISH_SENSOR_SDA */
Chris Wang5547c372017-10-05 21:57:16 +0800174 PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800175 /* D6 : ISH_I2C0_SCL ==> CHP1_I2C_ISH_SENSOR_SCL */
Chris Wang5547c372017-10-05 21:57:16 +0800176 PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1),
177 /* D7 : ISH_I2C1_SDA ==> NC */
178 PAD_CFG_NC(GPP_D7),
179 /* D8 : ISH_I2C1_SCL ==> NC */
180 PAD_CFG_NC(GPP_D8),
Chris Wangcb259742017-10-26 18:40:11 +0800181 /* D9 : ISH_SPI_CS# ==> CHP1_HEADSET_INT_L */
Naveen Manohar5bcb23e2017-11-04 04:00:12 +0530182 PAD_CFG_GPI_APIC(GPP_D9, 20K_PU, DEEP),
Chris Wangcb259742017-10-26 18:40:11 +0800183 /* D10 : ISH_SPI_CLK ==> NC */
184 PAD_CFG_NC(GPP_D10),
185 /* D11 : ISH_SPI_MISO ==> NC */
186 PAD_CFG_NC(GPP_D11),
Chris Wang5547c372017-10-05 21:57:16 +0800187 /* D12 : ISH_SPI_MOSI ==> NC */
188 PAD_CFG_NC(GPP_D12),
189 /* D13 : ISH_UART0_RXD ==> NC */
190 PAD_CFG_NC(GPP_D13),
191 /* D14 : ISH_UART0_TXD ==> NC */
192 PAD_CFG_NC(GPP_D14),
193 /* D15 : ISH_UART0_RTS# ==> NC */
194 PAD_CFG_NC(GPP_D15),
195 /* D16 : ISH_UART0_CTS# ==> NC */
196 PAD_CFG_NC(GPP_D16),
197 /* D17 : DMIC_CLK1 */
198 PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
199 /* D18 : DMIC_DATA1 */
200 PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
201 /* D19 : DMIC_CLK0 */
202 PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
203 /* D20 : DMIC_DATA0 */
204 PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
205 /* D21 : SPI1_IO2 ==> NC */
206 PAD_CFG_NC(GPP_D21),
Chris Wangcb259742017-10-26 18:40:11 +0800207 /* D22 : SPI1_IO3 ==> CHP1_BOOT_BEEP_OVERRIDE */
Chris Wang5547c372017-10-05 21:57:16 +0800208 PAD_CFG_GPO(GPP_D22, 1, DEEP),
Chris Wangcb259742017-10-26 18:40:11 +0800209 /* D23 : I2S_MCLK ==> CHP1_I2S_MCLK */
Chris Wang5547c372017-10-05 21:57:16 +0800210 PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
211
Chris Wangcb259742017-10-26 18:40:11 +0800212 /* E0 : SATAXPCI0 ==> CHP3_HAVEN_INT_L */
Chris Wang5547c372017-10-05 21:57:16 +0800213 PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
214 /* E1 : SATAXPCIE1 ==> NC */
215 PAD_CFG_NC(GPP_E1),
216 /* E2 : SATAXPCIE2 ==> NC */
217 PAD_CFG_NC(GPP_E2),
Chris Wangcb259742017-10-26 18:40:11 +0800218 /* E3 : CPU_GP0 ==> NC */
219 PAD_CFG_NC(GPP_E3),
Chris Wang5547c372017-10-05 21:57:16 +0800220 /* E4 : SATA_DEVSLP0 ==> NC */
221 PAD_CFG_NC(GPP_E4),
222 /* E5 : SATA_DEVSLP1 ==> NC */
223 PAD_CFG_NC(GPP_E5),
224 /* E6 : SATA_DEVSLP2 ==> NC */
225 PAD_CFG_NC(GPP_E6),
Chris Wangcb259742017-10-26 18:40:11 +0800226 /* E7 : CPU_GP1 ==> CHP3_TSP_INT_L */
Chris Wang5547c372017-10-05 21:57:16 +0800227 PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
228 /* E8 : SATALED# ==> NC */
229 PAD_CFG_NC(GPP_E8),
Chris Wangcb259742017-10-26 18:40:11 +0800230 /* E9 : USB2_OCO# ==> USB3_C1_OC1_L */
Chris Wang5547c372017-10-05 21:57:16 +0800231 PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800232 /* E10 : USB2_OC1# ==> USB3_C0_OC0_L */
Chris Wang5547c372017-10-05 21:57:16 +0800233 PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800234 /* E11 : USB2_OC2# ==> NC */
235 PAD_CFG_NC(GPP_E11),
Chris Wang5547c372017-10-05 21:57:16 +0800236 /* E12 : USB2_OC3# ==> USB2_OC3_L */
237 PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800238 /* E13 : DDPB_HPD0 ==> KBC3_USB_C0_DP_HPD */
Chris Wang5547c372017-10-05 21:57:16 +0800239 PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800240 /* E14 : DDPC_HPD1 ==> KBC3_USB_C1_DP_HPD */
Chris Wang5547c372017-10-05 21:57:16 +0800241 PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800242 /* E15 : DDPD_HPD2 ==> CPU3_SD_CD_L */
Chris Wang5547c372017-10-05 21:57:16 +0800243 PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),
Chris Wangcb259742017-10-26 18:40:11 +0800244 /* E16 : DDPE_HPD3 ==> NC(TP766) */
Chris Wang5547c372017-10-05 21:57:16 +0800245 PAD_CFG_NC(GPP_E16),
246 /* E17 : EDP_HPD */
247 PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
248 /* E18 : DDPB_CTRLCLK ==> NC */
249 PAD_CFG_NC(GPP_E18),
250 /* E19 : DDPB_CTRLDATA ==> NC */
251 PAD_CFG_NC(GPP_E19),
252 /* E20 : DDPC_CTRLCLK ==> NC */
253 PAD_CFG_NC(GPP_E20),
254 /* E21 : DDPC_CTRLDATA ==> NC */
255 PAD_CFG_NC(GPP_E21),
256 /* E22 : DDPD_CTRLCLK ==> NC */
257 PAD_CFG_NC(GPP_E22),
258 /* E23 : DDPD_CTRLDATA ==> NC */
259 PAD_CFG_NC(GPP_E23),
260
261 /* The next 4 pads are for bit banging the amplifiers, default to I2S */
Chris Wangcb259742017-10-26 18:40:11 +0800262 /* F0 : I2S2_SCLK ==> CHP1_I2S2_SCLK_SPKR_R */
Chris Wang5547c372017-10-05 21:57:16 +0800263 PAD_CFG_GPI(GPP_F0, NONE, DEEP),
Chris Wangcb259742017-10-26 18:40:11 +0800264 /* F1 : I2S2_SFRM ==> CHP1_I2S2_SFRM_SPKR_R*/
Chris Wang5547c372017-10-05 21:57:16 +0800265 PAD_CFG_GPI(GPP_F1, NONE, DEEP),
Chris Wangcb259742017-10-26 18:40:11 +0800266 /* F2 : I2S2_TXD ==> CHP1_I2S2_PCH_TX_SPKR_RX_R */
Chris Wang5547c372017-10-05 21:57:16 +0800267 PAD_CFG_GPI(GPP_F2, NONE, DEEP),
Furquan Shaikhcbb62342017-12-17 02:56:14 -0800268 /* F3 : I2S2_RXD ==> NC */
269 PAD_CFG_NC(GPP_F3),
Chris Wangcb259742017-10-26 18:40:11 +0800270 /* F4 : I2C2_SDA ==> CHP1_I2C2_CAM_PMIC_SDA */
Chris Wang5547c372017-10-05 21:57:16 +0800271 PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800272 /* F5 : I2C2_SCL ==> CHP1_I2C2_CAM_PMIC_SCL */
Chris Wang5547c372017-10-05 21:57:16 +0800273 PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800274 /* F6 : I2C3_SDA ==> CHP1_I2C3_DIG_SDA */
275 PAD_CFG_NF_1V8(GPP_F6, 5K_PU, DEEP, NF1),
276 /* F7 : I2C3_SCL ==> CHP1_I2C3_DIG_SCL */
277 PAD_CFG_NF_1V8(GPP_F7, 5K_PU, DEEP, NF1),
278 /* F8 : I2C4_SDA ==> CHP1_I2C4_TP_SDA */
Chris Wang5547c372017-10-05 21:57:16 +0800279 PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800280 /* F9 : I2C4_SCL ==> CHP1_I2C4_TP_SCL */
Chris Wang5547c372017-10-05 21:57:16 +0800281 PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800282 /* F10 : I2C5_SDA ==> CHP1_I2C5_AUDIO_SDA */
Chris Wang5547c372017-10-05 21:57:16 +0800283 PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800284 /* F11 : I2C5_SCL ==> CHP1_I2C5_AUDIO_SCL */
Chris Wang5547c372017-10-05 21:57:16 +0800285 PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1),
286 /* F12 : EMMC_CMD */
287 PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
288 /* F13 : EMMC_DATA0 */
289 PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
290 /* F14 : EMMC_DATA1 */
291 PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
292 /* F15 : EMMC_DATA2 */
293 PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
294 /* F16 : EMMC_DATA3 */
295 PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
296 /* F17 : EMMC_DATA4 */
297 PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
298 /* F18 : EMMC_DATA5 */
299 PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
300 /* F19 : EMMC_DATA6 */
301 PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
302 /* F20 : EMMC_DATA7 */
303 PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
304 /* F21 : EMMC_RCLK */
305 PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
306 /* F22 : EMMC_CLK */
307 PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
308 /* F23 : RSVD ==> NC */
309 PAD_CFG_NC(GPP_F23),
310
311 /* G0 : SD_CMD */
312 PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
313 /* G1 : SD_DATA0 */
314 PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
315 /* G2 : SD_DATA1 */
316 PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
317 /* G3 : SD_DATA2 */
318 PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
319 /* G4 : SD_DATA3 */
320 PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
321 /* G5 : SD_CD# */
322 PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
323 /* G6 : SD_CLK */
324 PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
325 /* G7 : SD_WP */
326 PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
327
Chris Wangcb259742017-10-26 18:40:11 +0800328 /* GPD0: BATLOW# ==> CHP3_BATLOW# */
Chris Wang5547c372017-10-05 21:57:16 +0800329 PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800330 /* GPD1: ACPRESENT ==> KBC3_AC_PRESENT */
Chris Wang5547c372017-10-05 21:57:16 +0800331 PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800332 /* GPD2: LAN_WAKE# ==> KBC3_PCH_WAKE_L */
Chris Wang5547c372017-10-05 21:57:16 +0800333 PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800334 /* GPD3: PWRBTN# ==> KBC3_PWRBTN_L */
Chris Wang5547c372017-10-05 21:57:16 +0800335 PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800336 /* GPD4: SLP_S3# ==> CHP3_SLPS3_L */
Chris Wang5547c372017-10-05 21:57:16 +0800337 PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800338 /* GPD5: SLP_S4# ==> CHP3_SLPS4_L */
Chris Wang5547c372017-10-05 21:57:16 +0800339 PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800340 /* GPD6: SLP_A# ==> NC(TP725) */
Chris Wang5547c372017-10-05 21:57:16 +0800341 PAD_CFG_NC(GPD6),
342 /* GPD7: RSVD ==> NC */
343 PAD_CFG_NC(GPD7),
Chris Wangcb259742017-10-26 18:40:11 +0800344 /* GPD8: SUSCLK ==> CHP3_SUSCLK */
Chris Wang5547c372017-10-05 21:57:16 +0800345 PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
Chris Wangcb259742017-10-26 18:40:11 +0800346 /* GPD9: SLP_WLAN# ==> NC(TP724) */
Chris Wang5547c372017-10-05 21:57:16 +0800347 PAD_CFG_NC(GPD9),
Chris Wangcb259742017-10-26 18:40:11 +0800348 /* GPD10: SLP_S5# ==> NC(TP742) */
Chris Wang5547c372017-10-05 21:57:16 +0800349 PAD_CFG_NC(GPD10),
350 /* GPD11: LANPHYC ==> NC */
351 PAD_CFG_NC(GPD11),
352};
353
354/* Early pad configuration in bootblock */
355static const struct pad_config early_gpio_table[] = {
Chris Wang5547c372017-10-05 21:57:16 +0800356 /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
357 PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
358 /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
359 PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
Chris Wang5547c372017-10-05 21:57:16 +0800360
361 /* Ensure UART pins are in native mode for H1. */
362 /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
363 PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
364 /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
365 PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
366
367 /* C23 : UART2_CTS# ==> PCH_WP */
368 PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
369
370 /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
371 PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
372};
373
374const struct pad_config *variant_gpio_table(size_t *num)
375{
376 *num = ARRAY_SIZE(gpio_table);
377 return gpio_table;
378}
379
380const struct pad_config *variant_early_gpio_table(size_t *num)
381{
382 *num = ARRAY_SIZE(early_gpio_table);
383 return early_gpio_table;
384}