blob: 6946b38f14affa6c8170f5586c7f1eb2989373ba [file] [log] [blame]
Chris Wang5547c372017-10-05 21:57:16 +08001chip soc/intel/skylake
2
3 # Deep Sx states
4 register "deep_s3_enable_ac" = "0"
Furquan Shaikhd37107e2017-11-08 11:28:10 -08005 register "deep_s3_enable_dc" = "0"
Chris Wang5547c372017-10-05 21:57:16 +08006 register "deep_s5_enable_ac" = "1"
7 register "deep_s5_enable_dc" = "1"
Furquan Shaikh9d867af2017-12-03 21:45:47 -08008 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
Chris Wang5547c372017-10-05 21:57:16 +08009
10 # GPE configuration
11 # Note that GPE events called out in ASL code rely on this
12 # route. i.e. If this route changes then the affected GPE
13 # offset bits also need to be changed.
14 register "gpe0_dw0" = "GPP_B"
15 register "gpe0_dw1" = "GPP_D"
16 register "gpe0_dw2" = "GPP_E"
17
18 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
19 register "gen1_dec" = "0x00fc0801"
20 register "gen2_dec" = "0x000c0201"
21 # EC memory map range is 0x900-0x9ff
22 register "gen3_dec" = "0x00fc0901"
23
Seunghwan Kim3f0c7242018-02-13 16:58:00 +090024 # Enable DPTF
25 register "dptf_enable" = "1"
26
Chris Wang5547c372017-10-05 21:57:16 +080027 # Enable S0ix
28 register "s0ix_enable" = "1"
29
30 # FSP Configuration
31 register "ProbelessTrace" = "0"
32 register "EnableLan" = "0"
33 register "EnableSata" = "0"
34 register "SataSalpSupport" = "0"
35 register "SataMode" = "0"
36 register "SataPortsEnable[0]" = "0"
37 register "EnableAzalia" = "1"
38 register "DspEnable" = "1"
39 register "IoBufferOwnership" = "3"
40 register "EnableTraceHub" = "0"
41 register "XdciEnable" = "0"
42 register "SsicPortEnable" = "0"
43 register "SmbusEnable" = "1"
Andy Yehbc81b672017-12-14 13:14:35 +080044 register "Cio2Enable" = "1"
45 register "SaImguEnable" = "1"
Chris Wang5547c372017-10-05 21:57:16 +080046 register "ScsEmmcEnabled" = "1"
47 register "ScsEmmcHs400Enabled" = "1"
48 register "ScsSdCardEnabled" = "2"
49 register "IshEnable" = "0"
50 register "PttSwitch" = "0"
51 register "InternalGfx" = "1"
52 register "SkipExtGfxScan" = "1"
53 register "Device4Enable" = "1"
54 register "HeciEnabled" = "0"
55 register "FspSkipMpInit" = "1"
56 register "SaGv" = "3"
57 register "SerialIrqConfigSirqEnable" = "1"
58 register "PmConfigSlpS3MinAssert" = "2" # 50ms
59 register "PmConfigSlpS4MinAssert" = "1" # 1s
60 register "PmConfigSlpSusMinAssert" = "1" # 500ms
61 register "PmConfigSlpAMinAssert" = "3" # 2s
62 register "PmTimerDisabled" = "1"
63
64 register "pirqa_routing" = "PCH_IRQ11"
65 register "pirqb_routing" = "PCH_IRQ10"
66 register "pirqc_routing" = "PCH_IRQ11"
67 register "pirqd_routing" = "PCH_IRQ11"
68 register "pirqe_routing" = "PCH_IRQ11"
69 register "pirqf_routing" = "PCH_IRQ11"
70 register "pirqg_routing" = "PCH_IRQ11"
71 register "pirqh_routing" = "PCH_IRQ11"
72
Chris Wang51de1802017-11-24 13:43:50 +080073 # VR Slew rate setting for improving audible noise
74 register "AcousticNoiseMitigation" = "1"
75 register "FastPkgCRampDisableIa" = "1"
76 register "FastPkgCRampDisableGt" = "1"
77 register "FastPkgCRampDisableSa" = "1"
78 register "SlowSlewRateForIa" = "3" # Fast/16
79 register "SlowSlewRateForGt" = "3" # Fast/16
Seunghwan Kim3dd88f12018-02-27 14:27:26 +090080 register "SlowSlewRateForSa" = "2" # Fast/8
81
Chris Wang5547c372017-10-05 21:57:16 +080082 # VR Settings Configuration for 4 Domains
83 #+----------------+-------+-------+-------+-------+
84 #| Domain/Setting | SA | IA | GTUS | GTS |
85 #+----------------+-------+-------+-------+-------+
86 #| Psi1Threshold | 20A | 20A | 20A | 20A |
87 #| Psi2Threshold | 2A | 2A | 2A | 2A |
88 #| Psi3Threshold | 1A | 1A | 1A | 1A |
89 #| Psi3Enable | 1 | 1 | 1 | 1 |
90 #| Psi4Enable | 1 | 1 | 1 | 1 |
91 #| ImonSlope | 0 | 0 | 0 | 0 |
92 #| ImonOffset | 0 | 0 | 0 | 0 |
93 #| IccMax | 5A | 24A | 24A | 24A |
94 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
95 #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 |
96 #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 |
97 #+----------------+-------+-------+-------+-------+
98 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
99 .vr_config_enable = 1,
100 .psi1threshold = VR_CFG_AMP(20),
101 .psi2threshold = VR_CFG_AMP(2),
102 .psi3threshold = VR_CFG_AMP(1),
103 .psi3enable = 1,
104 .psi4enable = 1,
105 .imon_slope = 0x0,
106 .imon_offset = 0x0,
107 .icc_max = VR_CFG_AMP(5),
108 .voltage_limit = 1520,
109 .ac_loadline = 1500,
110 .dc_loadline = 1430,
111 }"
112
113 register "domain_vr_config[VR_IA_CORE]" = "{
114 .vr_config_enable = 1,
115 .psi1threshold = VR_CFG_AMP(20),
116 .psi2threshold = VR_CFG_AMP(2),
117 .psi3threshold = VR_CFG_AMP(1),
118 .psi3enable = 1,
119 .psi4enable = 1,
120 .imon_slope = 0x0,
121 .imon_offset = 0x0,
122 .icc_max = VR_CFG_AMP(24),
123 .voltage_limit = 1520,
124 .ac_loadline = 570,
125 .dc_loadline = 483,
126 }"
127
128 register "domain_vr_config[VR_GT_UNSLICED]" = "{
129 .vr_config_enable = 1,
130 .psi1threshold = VR_CFG_AMP(20),
131 .psi2threshold = VR_CFG_AMP(2),
132 .psi3threshold = VR_CFG_AMP(1),
133 .psi3enable = 1,
134 .psi4enable = 1,
135 .imon_slope = 0x0,
136 .imon_offset = 0x0,
137 .icc_max = VR_CFG_AMP(24),
138 .voltage_limit = 1520,
139 .ac_loadline = 550,
140 .dc_loadline = 420,
141 }"
142
143 register "domain_vr_config[VR_GT_SLICED]" = "{
144 .vr_config_enable = 1,
145 .psi1threshold = VR_CFG_AMP(20),
146 .psi2threshold = VR_CFG_AMP(2),
147 .psi3threshold = VR_CFG_AMP(1),
148 .psi3enable = 1,
149 .psi4enable = 1,
150 .imon_slope = 0x0,
151 .imon_offset = 0x0,
152 .icc_max = VR_CFG_AMP(24),
153 .voltage_limit = 1520,
154 .ac_loadline = 550,
155 .dc_loadline = 420,
156 }"
157
158 # Enable Root port 1.
159 register "PcieRpEnable[0]" = "1"
160 # Enable CLKREQ#
161 register "PcieRpClkReqSupport[0]" = "1"
162 # RP 1 uses SRCCLKREQ1#
163 register "PcieRpClkReqNumber[0]" = "1"
Divya Chellape7fb7ce2017-12-19 20:16:50 +0530164 # RP 1 uses uses CLK SRC 1
165 register "PcieRpClkSrcNumber[0]" = "1"
Furquan Shaikh9c12e902017-12-17 20:31:18 -0800166 # RP 1, Enable Advanced Error Reporting
167 register "PcieRpAdvancedErrorReporting[0]" = "1"
168 # RP 1, Enable Latency Tolerance Reporting Mechanism
169 register "PcieRpLtrEnable[0]" = "1"
Chris Wang5547c372017-10-05 21:57:16 +0800170
171 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
sh.kim35325e12017-12-01 16:09:50 +0900172 register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port
173 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
Chris Wang5547c372017-10-05 21:57:16 +0800174 register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
sh.kim35325e12017-12-01 16:09:50 +0900175 register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1
176 register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera
Chris Wang5547c372017-10-05 21:57:16 +0800177
178 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
179 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
180 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
181 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
182
183 # Touchscreen
184 register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
Chris Wang5220e5f2017-11-24 14:00:48 +0800185 register "i2c[0]" = "{
186 .speed = I2C_SPEED_FAST,
187 .speed_config[0] = {
188 .speed = I2C_SPEED_FAST,
189 .scl_lcnt = 180,
190 .scl_hcnt = 90,
191 .sda_hold = 36,
192 },
193 }"
Chris Wang5547c372017-10-05 21:57:16 +0800194
195 # H1
196 register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
197 # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
198 # for TPM communication before memory is up.
199 register "i2c[1]" = "{
200 .early_init = 1,
Chris Wang5220e5f2017-11-24 14:00:48 +0800201 .speed = I2C_SPEED_FAST,
202 .speed_config[0] = {
203 .speed = I2C_SPEED_FAST,
204 .scl_lcnt = 185,
205 .scl_hcnt = 90,
206 .sda_hold = 36,
207 },
Chris Wang5547c372017-10-05 21:57:16 +0800208 }"
209
210 # Trackpad
211 register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
Chris Wang5220e5f2017-11-24 14:00:48 +0800212 register "i2c[2]" = "{
213 .speed = I2C_SPEED_FAST,
214 .speed_config[0] = {
215 .speed = I2C_SPEED_FAST,
216 .scl_lcnt = 190,
217 .scl_hcnt = 100,
218 .sda_hold = 36,
219 },
220 }"
Chris Wang5547c372017-10-05 21:57:16 +0800221
222 # Pen
223 register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
Chris Wang5220e5f2017-11-24 14:00:48 +0800224 register "i2c[3]" = "{
225 .speed = I2C_SPEED_FAST,
226 .speed_config[0] = {
227 .speed = I2C_SPEED_FAST,
228 .scl_lcnt = 185,
229 .scl_hcnt = 90,
230 .sda_hold = 36,
231 },
232 }"
Chris Wang5547c372017-10-05 21:57:16 +0800233
234 # Camera
235 register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
Chris Wang5220e5f2017-11-24 14:00:48 +0800236 register "i2c[4]" = "{
237 .speed = I2C_SPEED_FAST,
238 .speed_config[0] = {
239 .speed = I2C_SPEED_FAST,
240 .scl_lcnt = 190,
241 .scl_hcnt = 100,
242 .sda_hold = 36,
243 },
244 }"
Chris Wang5547c372017-10-05 21:57:16 +0800245
246 # Audio
247 register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"
Chris Wang5220e5f2017-11-24 14:00:48 +0800248 register "i2c[5]" = "{
249 .speed = I2C_SPEED_FAST,
250 .speed_config[0] = {
251 .speed = I2C_SPEED_FAST,
252 .scl_lcnt = 190,
253 .scl_hcnt = 100,
254 .sda_hold = 36,
255 },
256 }"
Chris Wang5547c372017-10-05 21:57:16 +0800257
258 # Must leave UART0 enabled or SD/eMMC will not work as PCI
259 register "SerialIoDevMode" = "{
260 [PchSerialIoIndexI2C0] = PchSerialIoPci,
261 [PchSerialIoIndexI2C1] = PchSerialIoPci,
262 [PchSerialIoIndexI2C2] = PchSerialIoPci,
263 [PchSerialIoIndexI2C3] = PchSerialIoPci,
264 [PchSerialIoIndexI2C4] = PchSerialIoPci,
265 [PchSerialIoIndexI2C5] = PchSerialIoPci,
266 [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
267 [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
Furquan Shaikh8a1f0952018-01-24 13:14:33 -0800268 [PchSerialIoIndexUart0] = PchSerialIoSkipInit,
Chris Wang5547c372017-10-05 21:57:16 +0800269 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
270 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
271 }"
272
273 register "speed_shift_enable" = "1"
Naresh G Solanki5b131e22018-02-14 20:31:18 +0530274 register "psys_pmax" = "45"
Chris Wang5547c372017-10-05 21:57:16 +0800275 # PL2 override 15W for KBL-Y
276 register "tdp_pl2_override" = "15"
277 register "tcc_offset" = "10" # TCC of 90C
278
279 # Use default SD card detect GPIO configuration
280 register "sdcard_cd_gpio_default" = "GPP_E15"
281
282 # Lock Down
283 register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
284
Furquan Shaikh39d30212018-03-01 18:08:06 -0800285 # PCH Trip Temperature in degree C
286 register "pch_trip_temp" = "75"
287
Chris Wang5547c372017-10-05 21:57:16 +0800288 device cpu_cluster 0 on
289 device lapic 0 on end
290 end
291 device domain 0 on
292 device pci 00.0 on end # Host Bridge
293 device pci 02.0 on end # Integrated Graphics Device
294 device pci 14.0 on end # USB xHCI
295 device pci 14.1 off end # USB xDCI (OTG)
296 device pci 14.2 on end # Thermal Subsystem
Chris Wang94dc50e2017-11-28 16:33:27 +0800297 device pci 15.0 on
298 chip drivers/i2c/hid
299 register "generic.hid" = ""SYTS7813""
300 register "generic.desc" = ""Synaptics Touchscreen""
301 register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
302 register "generic.probed" = "1"
303 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"
304 register "generic.enable_delay_ms" = "45"
305 register "generic.has_power_resource" = "1"
306 register "generic.disable_gpio_export_in_crs" = "1"
307 register "hid_desc_reg_offset" = "0x20"
308 device i2c 20 on end
309 end
310 end # I2C #0
Chris Wang5547c372017-10-05 21:57:16 +0800311 device pci 15.1 on
312 chip drivers/i2c/tpm
313 register "hid" = ""GOOG0005""
314 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
315 device i2c 50 on end
316 end
317 end # I2C #1
318 device pci 15.2 on end # I2C #2
Seunghwan Kim533ea7a2017-12-28 10:40:35 +0900319 device pci 15.3 on
320 chip drivers/i2c/hid
321 register "generic.hid" = ""ACPI0C50""
322 register "generic.cid" = ""PNP0C50""
323 register "generic.desc" = ""Digitizer device""
324 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A22_IRQ)"
325 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C9)"
326 register "generic.has_power_resource" = "1"
327 register "generic.disable_gpio_export_in_crs" = "1"
328 register "generic.wake" = "GPE0_DW0_21"
329 register "hid_desc_reg_offset" = "0x1"
330 device i2c 0x9 on end
331 end
Furquan Shaikhbb1e5392018-01-11 20:29:38 -0800332 chip drivers/generic/gpio_keys
333 register "name" = ""PENH""
334 register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_B19)"
335 register "key.dev_name" = ""EJCT""
336 register "key.linux_code" = "SW_PEN_INSERTED"
337 register "key.linux_input_type" = "EV_SW"
338 register "key.label" = ""pen_eject""
339 device generic 0 on end
340 end
Seunghwan Kim533ea7a2017-12-28 10:40:35 +0900341 end # I2C #3
Chris Wang5547c372017-10-05 21:57:16 +0800342 device pci 16.0 on end # Management Engine Interface 1
343 device pci 16.1 off end # Management Engine Interface 2
344 device pci 16.2 off end # Management Engine IDE-R
345 device pci 16.3 off end # Management Engine KT Redirection
346 device pci 16.4 off end # Management Engine Interface 3
347 device pci 17.0 off end # SATA
348 device pci 19.0 on end # UART #2
Naveen Manohar5bcb23e2017-11-04 04:00:12 +0530349 device pci 19.1 on
Naveen Manohar1533dfd2017-10-12 15:50:21 +0900350 chip drivers/generic/max98357a
351 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
352 register "sdmode_delay" = "5"
353 device generic 0 on end
354 end
Naveen Manohar5bcb23e2017-11-04 04:00:12 +0530355 chip drivers/i2c/da7219
356 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)"
357 register "btn_cfg" = "50"
358 register "mic_det_thr" = "500"
359 register "jack_ins_deb" = "20"
360 register "jack_det_rate" = ""32ms_64ms""
361 register "jack_rem_deb" = "1"
362 register "a_d_btn_thr" = "0xa"
363 register "d_b_btn_thr" = "0x16"
364 register "b_c_btn_thr" = "0x21"
365 register "c_mic_btn_thr" = "0x3e"
366 register "btn_avg" = "4"
367 register "adc_1bit_rpt" = "1"
368 register "micbias_lvl" = "2600"
369 register "mic_amp_in_sel" = ""diff""
370 device i2c 1A on end
371 end
372 end # I2C #5
Chris Wang36e40e42017-10-26 19:04:57 +0800373 device pci 19.2 on
374 chip drivers/i2c/generic
375 register "hid" = ""ELAN0000""
376 register "desc" = ""ELAN Touchpad""
377 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
378 register "wake" = "GPE0_DW0_05"
379 device i2c 15 on end
380 end
381 end # I2C #4
Chris Wang5547c372017-10-05 21:57:16 +0800382 device pci 1c.0 on
383 chip drivers/intel/wifi
Seunghwan Kimdf2ae962018-02-01 14:33:04 +0900384 register "wake" = "GPE0_DW0_00"
Chris Wang5547c372017-10-05 21:57:16 +0800385 device pci 00.0 on end
386 end
387 end # PCI Express Port 1
388 device pci 1c.1 off end # PCI Express Port 2
389 device pci 1c.2 off end # PCI Express Port 3
390 device pci 1c.3 off end # PCI Express Port 4
391 device pci 1c.4 off end # PCI Express Port 5
392 device pci 1c.5 off end # PCI Express Port 6
393 device pci 1c.6 off end # PCI Express Port 7
394 device pci 1c.7 off end # PCI Express Port 8
395 device pci 1d.0 off end # PCI Express Port 9
396 device pci 1d.1 off end # PCI Express Port 10
397 device pci 1d.2 off end # PCI Express Port 11
398 device pci 1d.3 off end # PCI Express Port 12
399 device pci 1e.0 on end # UART #0
400 device pci 1e.1 off end # UART #1
401 device pci 1e.2 off end # GSPI #0
402 device pci 1e.3 off end # GSPI #1
403 device pci 1e.4 on end # eMMC
404 device pci 1e.5 off end # SDIO
405 device pci 1e.6 on end # SDCard
406 device pci 1f.0 on
407 chip ec/google/chromeec
408 device pnp 0c09.0 on end
409 end
410 end # LPC Interface
411 device pci 1f.1 on end # P2SB
412 device pci 1f.2 on end # Power Management Controller
413 device pci 1f.3 on end # Intel HDA
414 device pci 1f.4 on end # SMBus
415 device pci 1f.5 on end # PCH SPI
416 device pci 1f.6 off end # GbE
417 end
418end