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Gabe Blackd3163ab2013-05-16 05:53:40 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Samsung Electronics
5 * Copyright 2013 Google Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Gabe Blackd3163ab2013-05-16 05:53:40 -070015 */
16
Julius Werner80af4422014-10-20 13:18:56 -070017#include <console/console.h>
18#include <soc/clk.h>
19#include <soc/dmc.h>
20#include <soc/gpio.h>
21#include <soc/setup.h>
Gabe Blackd3163ab2013-05-16 05:53:40 -070022#include <stddef.h>
23#include <stdlib.h>
Gabe Blackd3163ab2013-05-16 05:53:40 -070024
Ronald G. Minniche6af9292013-06-03 13:03:50 -070025const struct mem_timings mem_timings = {
Gabe Blackd3163ab2013-05-16 05:53:40 -070026 .mem_manuf = MEM_MANUF_SAMSUNG,
27 .mem_type = DDR_MODE_DDR3,
28 .frequency_mhz = 800,
Gabe Blackd3163ab2013-05-16 05:53:40 -070029 .direct_cmd_msr = {
David Hendricks42b1b802013-08-26 15:12:12 -070030 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
31 0x00000c70
Gabe Blackd3163ab2013-05-16 05:53:40 -070032 },
33 .timing_ref = 0x000000bb,
Ronald G. Minniche6af9292013-06-03 13:03:50 -070034 .timing_row = 0x6836650f,
Gabe Blackd3163ab2013-05-16 05:53:40 -070035 .timing_data = 0x3630580b,
Ronald G. Minniche6af9292013-06-03 13:03:50 -070036 .timing_power = 0x41000a26,
Gabe Blackd3163ab2013-05-16 05:53:40 -070037 .phy0_dqs = 0x08080808,
38 .phy1_dqs = 0x08080808,
39 .phy0_dq = 0x08080808,
40 .phy1_dq = 0x08080808,
41 .phy0_tFS = 0x8,
42 .phy1_tFS = 0x8,
43 .phy0_pulld_dqs = 0xf,
44 .phy1_pulld_dqs = 0xf,
45
46 .lpddr3_ctrl_phy_reset = 0x1,
47 .ctrl_start_point = 0x10,
48 .ctrl_inc = 0x10,
49 .ctrl_start = 0x1,
50 .ctrl_dll_on = 0x1,
51 .ctrl_ref = 0x8,
52
53 .ctrl_force = 0x1a,
54 .ctrl_rdlat = 0x0b,
55 .ctrl_bstlen = 0x08,
56
57 .fp_resync = 0x8,
58 .iv_size = 0x7,
59 .dfi_init_start = 1,
60 .aref_en = 1,
61
62 .rd_fetch = 0x3,
63
David Hendricks42b1b802013-08-26 15:12:12 -070064 .zq_mode_dds = 0x7,
Gabe Blackd3163ab2013-05-16 05:53:40 -070065 .zq_mode_term = 0x1,
66 .zq_mode_noterm = 1,
67
68 /*
69 * Dynamic Clock: Always Running
70 * Memory Burst length: 8
71 * Number of chips: 1
72 * Memory Bus width: 32 bit
73 * Memory Type: DDR3
74 * Additional Latancy for PLL: 0 Cycle
75 */
76 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
77 DMC_MEMCONTROL_DPWRDN_DISABLE |
78 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
Ronald G. Minniche6af9292013-06-03 13:03:50 -070079 DMC_MEMCONTROL_DSREF_DISABLE |
Gabe Blackd3163ab2013-05-16 05:53:40 -070080 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
81 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
82 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
David Hendricks72a42882013-08-23 15:25:07 -070083 DMC_MEMCONTROL_NUM_CHIP_1 |
Gabe Blackd3163ab2013-05-16 05:53:40 -070084 DMC_MEMCONTROL_BL_8 |
85 DMC_MEMCONTROL_PZQ_DISABLE |
86 DMC_MEMCONTROL_MRR_BYTE_7_0,
David Hendricks122b6d62013-08-29 14:05:21 -070087 /*
88 * For channel interleaving, the chip_base needs to be set to
89 * half the bus address. So for a base address of 0x2000_0000,
90 * the chip_base value is 0x20 without interleaving and 0x10
91 * with channel interleaving. See note in section 17.14.
92 */
93 .membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_1GB,
Ronald G. Minniche6af9292013-06-03 13:03:50 -070094 .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
Gabe Blackd3163ab2013-05-16 05:53:40 -070095 DMC_MEMCONFIGx_CHIP_COL_10 |
96 DMC_MEMCONFIGx_CHIP_ROW_15 |
97 DMC_MEMCONFIGx_CHIP_BANK_8,
Gabe Blackd3163ab2013-05-16 05:53:40 -070098 .prechconfig_tp_cnt = 0xff,
99 .dpwrdn_cyc = 0xff,
100 .dsref_cyc = 0xffff,
101 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
102 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
103 DMC_CONCONTROL_RD_FETCH_DISABLE |
Gabe Blackd3163ab2013-05-16 05:53:40 -0700104 DMC_CONCONTROL_AREF_EN_DISABLE |
105 DMC_CONCONTROL_IO_PD_CON_DISABLE,
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700106 .dmc_channels = 1,
David Hendricks72a42882013-08-23 15:25:07 -0700107 .chips_per_channel = 1,
108 .chips_to_configure = 1,
Gabe Blackd3163ab2013-05-16 05:53:40 -0700109 .send_zq_init = 1,
Gabe Blackd3163ab2013-05-16 05:53:40 -0700110 .gate_leveling_enable = 1,
Gabe Blackd3163ab2013-05-16 05:53:40 -0700111};