Blame - src/northbridge/amd/pi/Kconfig - coreboot

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Bruce Griffith	27ed80b	2014-08-15 11:46:25 -0600	[diff] [blame]	1	#
				2	# This file is part of the coreboot project.
				3	#
Marc Jones	aa31f99	2016-09-20 20:30:17 -0600	[diff] [blame]	4	# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc.
Bruce Griffith	27ed80b	2014-08-15 11:46:25 -0600	[diff] [blame]	5	#
				6	# This program is free software; you can redistribute it and/or modify
				7	# it under the terms of the GNU General Public License as published by
				8	# the Free Software Foundation; version 2 of the License.
				9	#
				10	# This program is distributed in the hope that it will be useful,
				11	# but WITHOUT ANY WARRANTY; without even the implied warranty of
				12	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
				13	# GNU General Public License for more details.
				14	#
Bruce Griffith	27ed80b	2014-08-15 11:46:25 -0600	[diff] [blame]	15
Kyösti Mälkki	e4c17ce	2014-10-21 18:22:32 +0300	[diff] [blame]	16	config NORTHBRIDGE_AMD_PI
Martin Roth	595e777	2015-04-26 18:53:26 -0600	[diff] [blame]	17	bool
				18	default CPU_AMD_PI
Kyösti Mälkki	3bf3854	2014-12-18 22:22:04 +0200	[diff] [blame]	19	select LATE_CBMEM_INIT
Bruce Griffith	27ed80b	2014-08-15 11:46:25 -0600	[diff] [blame]	20
Kyösti Mälkki	e4c17ce	2014-10-21 18:22:32 +0300	[diff] [blame]	21	if NORTHBRIDGE_AMD_PI
				22
Ricardo Ribalda Delgado	a132892	2016-12-28 15:16:22 +0100	[diff] [blame]	23	config BOTTOMIO_POSITION
				24	hex "Bottom of 32-bit IO space"
				25	default 0xD0000000
				26	help
				27	If PCI peripherals with big BARs are connected to the system
				28	the bottom of the IO must be decreased to allocate such
				29	devices.
				30
				31	Declare the beginning of the 128MB-aligned MMIO region. This
				32	option is useful when PCI peripherals requesting large address
				33	ranges are present.
				34
Kyösti Mälkki	e4c17ce	2014-10-21 18:22:32 +0300	[diff] [blame]	35	config CONSOLE_VGA_MULTI
				36	bool
				37	default n
				38
				39	config S3_VGA_ROM_RUN
				40	bool
				41	default n
				42
Bruce Griffith	006364e	2014-10-22 03:33:49 -0600	[diff] [blame]	43	source src/northbridge/amd/pi/00630F01/Kconfig
Kyösti Mälkki	e4c17ce	2014-10-21 18:22:32 +0300	[diff] [blame]	44	source src/northbridge/amd/pi/00730F01/Kconfig
Marc Jones	aa31f99	2016-09-20 20:30:17 -0600	[diff] [blame]	45	source src/northbridge/amd/pi/00670F00/Kconfig
WANG Siyuan	0563941	2015-05-20 14:44:32 +0800	[diff] [blame]	46	source src/northbridge/amd/pi/00660F01/Kconfig
Kyösti Mälkki	e4c17ce	2014-10-21 18:22:32 +0300	[diff] [blame]	47
WANG Siyuan	2dcd0fc	2015-06-02 16:25:58 +0800	[diff] [blame]	48	config HW_MEM_HOLE_SIZEK
				49	hex
				50	default 0x200000
				51
				52	config HW_MEM_HOLE_SIZE_AUTO_INC
				53	bool
				54	default n
				55
				56	config RAMTOP
				57	hex
				58	default 0x1000000
				59
				60	config HEAP_SIZE
				61	hex
				62	default 0xc0000
				63
				64	config RAMBASE
				65	hex
				66	default 0x200000
				67
Kyösti Mälkki	e4c17ce	2014-10-21 18:22:32 +0300	[diff] [blame]	68	endif # NORTHBRIDGE_AMD_PI