blob: adcb41797e1d1efbe3cb1cfee2172ac7a22bfb78 [file] [log] [blame]
Renze Nicolaia688b7c2016-11-18 23:08:13 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/**
17 * @file
18 *
19 * AMD User options selection for a Brazos platform solution system
20 *
21 * This file is placed in the user's platform directory and contains the
22 * build option selections desired for that platform.
23 *
24 * For Information about this file, see @ref platforminstall.
25 *
26 */
27
28#include <stdlib.h>
29
30#include <vendorcode/amd/agesa/f15tn/AGESA.h>
31
32/* Include the files that instantiate the configuration definitions. */
33#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
34#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
35#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
36#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
37/* the next two headers depend on heapManager.h */
38#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
39#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
40/* These tables are optional and may be used to adjust memory timing settings */
41#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
42#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
43
Renze Nicolaia688b7c2016-11-18 23:08:13 +010044
45/* Select the CPU family. */
46#define INSTALL_FAMILY_10_SUPPORT FALSE
47#define INSTALL_FAMILY_12_SUPPORT FALSE
48#define INSTALL_FAMILY_14_SUPPORT FALSE
49#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
50
51/* Select the CPU socket type. */
52#define INSTALL_G34_SOCKET_SUPPORT FALSE
53#define INSTALL_C32_SOCKET_SUPPORT FALSE
54#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
55#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
56#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
57#define INSTALL_FS1_SOCKET_SUPPORT FALSE
58#define INSTALL_FM1_SOCKET_SUPPORT FALSE
59#define INSTALL_FP2_SOCKET_SUPPORT FALSE
60#define INSTALL_FT1_SOCKET_SUPPORT FALSE
61#define INSTALL_AM3_SOCKET_SUPPORT FALSE
62
63#define INSTALL_FM2_SOCKET_SUPPORT TRUE
64
65//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
66#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
67#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
68#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
69#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
70//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
71//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
72#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
73#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
74#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
75//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
76#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
77//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
78#define BLDOPT_REMOVE_SRAT FALSE //TRUE
79#define BLDOPT_REMOVE_SLIT FALSE //TRUE
80#define BLDOPT_REMOVE_WHEA FALSE //TRUE
81#define BLDOPT_REMOVE_CRAT TRUE
82#define BLDOPT_REMOVE_DMI TRUE
83//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
84//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
85//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
86//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
87//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
88//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
89
90//This element selects whether P-States should be forced to be independent,
91// as reported by the ACPI _PSD object. For single-link processors,
92// setting TRUE for OS to support this feature.
93
94//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
95
96#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
97#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
98/* Build configuration values here.
99 */
100#define BLDCFG_VRM_CURRENT_LIMIT 90000
101#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
102#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
103#define BLDCFG_PLAT_NUM_IO_APICS 3
104#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
105#define BLDCFG_MEM_INIT_PSTATE 0
106
107#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
108
109#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
110#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
111#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
112#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
113#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
114#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
115#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
116#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
117#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
118#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
119#define BLDCFG_MEMORY_POWER_DOWN TRUE
120#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
121#define BLDCFG_ONLINE_SPARE FALSE
122#define BLDCFG_BANK_SWIZZLE TRUE
123#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
124#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
125#define BLDCFG_DQS_TRAINING_CONTROL TRUE
126#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
127#define BLDCFG_USE_BURST_MODE FALSE
128#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
129#define BLDCFG_ENABLE_ECC_FEATURE FALSE
130#define BLDCFG_ECC_REDIRECTION FALSE
131#define BLDCFG_SCRUB_DRAM_RATE 0
132#define BLDCFG_SCRUB_L2_RATE 0
133#define BLDCFG_SCRUB_L3_RATE 0
134#define BLDCFG_SCRUB_IC_RATE 0
135#define BLDCFG_SCRUB_DC_RATE 0
136#define BLDCFG_ECC_SYMBOL_SIZE 4
137#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
138#define BLDCFG_ECC_SYNC_FLOOD FALSE
139#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
140#define BLDCFG_1GB_ALIGN FALSE
141#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
142#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
143#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
144
145#define BLDOPT_REMOVE_ALIB FALSE
146#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled
147#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
148#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
149#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
150
151#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
152#define BLDCFG_CFG_ABM_SUPPORT 0
153
154//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
155
156// Specify the default values for the VRM controlling the VDDNB plane.
157// If not specified, the values used for the core VRM will be applied
158//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
159//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
160//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
161//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
162//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
163//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
164
165#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
166
167#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
168#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
169
Martin Roth43927ba2017-06-24 21:54:33 -0600170#if IS_ENABLED(CONFIG_GFXUMA)
Elyes HAOUAS1d446342018-05-28 13:41:43 +0200171#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
172#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
173//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
174#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
175#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
Renze Nicolaia688b7c2016-11-18 23:08:13 +0100176#endif
177
178#define BLDCFG_IOMMU_SUPPORT TRUE
179
180#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
181//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
182//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
183//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
184
185/* Process the options...
186 * This file include MUST occur AFTER the user option selection settings
187 */
188/*
189 * Customized OEM build configurations for FCH component
190 */
191// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
192// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
193// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
194// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
195// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
196// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
197// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
198// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
199// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
200// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
201// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
202// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
203// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
204// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
205// #define BLDCFG_AZALIA_SSID 0x780D1022
206// #define BLDCFG_SMBUS_SSID 0x780B1022
207// #define BLDCFG_IDE_SSID 0x780C1022
208// #define BLDCFG_SATA_AHCI_SSID 0x78011022
209// #define BLDCFG_SATA_IDE_SSID 0x78001022
210// #define BLDCFG_SATA_RAID5_SSID 0x78031022
211// #define BLDCFG_SATA_RAID_SSID 0x78021022
212// #define BLDCFG_EHCI_SSID 0x78081022
213// #define BLDCFG_OHCI_SSID 0x78071022
214// #define BLDCFG_LPC_SSID 0x780E1022
215// #define BLDCFG_SD_SSID 0x78061022
216// #define BLDCFG_XHCI_SSID 0x78121022
217// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
218// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
219// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
220// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
221// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
222// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
223// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
224// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
225// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
226// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
227// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
228
229CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
230{
231 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
232 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
233 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
234 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
235 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
236 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
237 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
238 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
239 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
240 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
241 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
242 { CPU_LIST_TERMINAL }
243};
244
245#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
246
247 // This is the delivery package title, "BrazosPI"
248 // This string MUST be exactly 8 characters long
249#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
250
251 // This is the release version number of the AGESA component
252 // This string MUST be exactly 12 characters long
253#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
254
255/* MEMORY_BUS_SPEED */
256#define DDR400_FREQUENCY 200 ///< DDR 400
257#define DDR533_FREQUENCY 266 ///< DDR 533
258#define DDR667_FREQUENCY 333 ///< DDR 667
259#define DDR800_FREQUENCY 400 ///< DDR 800
260#define DDR1066_FREQUENCY 533 ///< DDR 1066
261#define DDR1333_FREQUENCY 667 ///< DDR 1333
262#define DDR1600_FREQUENCY 800 ///< DDR 1600
263#define DDR1866_FREQUENCY 933 ///< DDR 1866
264#define DDR2100_FREQUENCY 1050 ///< DDR 2100
265#define DDR2133_FREQUENCY 1066 ///< DDR 2133
266#define DDR2400_FREQUENCY 1200 ///< DDR 2400
267#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
268
269/* QUANDRANK_TYPE*/
270#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
271#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
272
273/* USER_MEMORY_TIMING_MODE */
274#define TIMING_MODE_AUTO 0 ///< Use best rate possible
275#define TIMING_MODE_LIMITED 1 ///< Set user top limit
276#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
277
278/* POWER_DOWN_MODE */
279#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
280#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
281
282/*
283 * Agesa optional capabilities selection.
284 * Uncomment and mark FALSE those features you wish to include in the build.
285 * Comment out or mark TRUE those features you want to REMOVE from the build.
286 */
287
288#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
289#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
290/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
291#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
292#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
293#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
294#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
295#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
296#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
297#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
298#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
299#define DFLT_HPET_BASE_ADDRESS 0xFED00000
300#define DFLT_SMI_CMD_PORT 0xB0
301#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
302#define DFLT_GEC_BASE_ADDRESS 0xFED61000
303#define DFLT_AZALIA_SSID 0x780D1022
304#define DFLT_SMBUS_SSID 0x780B1022
305#define DFLT_IDE_SSID 0x780C1022
306#define DFLT_SATA_AHCI_SSID 0x78011022
307#define DFLT_SATA_IDE_SSID 0x78001022
308#define DFLT_SATA_RAID5_SSID 0x78031022
309#define DFLT_SATA_RAID_SSID 0x78021022
310#define DFLT_EHCI_SSID 0x78081022
311#define DFLT_OHCI_SSID 0x78071022
312#define DFLT_LPC_SSID 0x780E1022
313#define DFLT_SD_SSID 0x78061022
314#define DFLT_XHCI_SSID 0x78121022
315#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
316#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
317#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1
318#define DFLT_FCH_GPP_PORT0_PRESENT TRUE
319#define DFLT_FCH_GPP_PORT1_PRESENT TRUE
320#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
321#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
322#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
323#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
324#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
325#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
326//#define BLDCFG_IR_PIN_CONTROL 0x33
327//#define FCH_NO_XHCI_SUPPORT FALSE
Renze Nicolai282c8322016-11-18 23:33:16 +0100328GPIO_CONTROL ms7721_m_gpio[] = {
Renze Nicolaia688b7c2016-11-18 23:08:13 +0100329// {183, Function1, PullUpB},
330 {-1}
331};
Renze Nicolai282c8322016-11-18 23:33:16 +0100332#define BLDCFG_FCH_GPIO_CONTROL_LIST (&ms7721_m_gpio[0])
Renze Nicolaia688b7c2016-11-18 23:08:13 +0100333
334// The following definitions specify the default values for various parameters in which there are
335// no clearly defined defaults to be used in the common file. The values below are based on product
336// and BKDG content, please consult the AGESA Memory team for consultation.
337#define DFLT_SCRUB_DRAM_RATE (0)
338#define DFLT_SCRUB_L2_RATE (0)
339#define DFLT_SCRUB_L3_RATE (0)
340#define DFLT_SCRUB_IC_RATE (0)
341#define DFLT_SCRUB_DC_RATE (0)
342#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
343#define DFLT_VRM_SLEW_RATE (5000)
344
345/* Moving this include up will break AGESA. */
Kyösti Mälkkic8e47422017-08-31 08:52:12 +0300346#include <PlatformInstall.h>