Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 2120e0e200d41e4b29d5e035d8ae5c219a54c495 / . / src / mainboard / google / falco / i915io.c
blob: aae7f29779fef3e8d029e149e2338950e6e38187 [file] [log] [blame]
Ronald G. Minnich2120e0e22013-10-09 15:53:43 -0700[diff] [blame^]1/*
2* This file is part of the coreboot project.
3*
4* Copyright 2013 Google Inc.
5*
6* This program is free software; you can redistribute it and/or modify
7* it under the terms of the GNU General Public License as published by
8* the Free Software Foundation; version 2 of the License.
9*
10* This program is distributed in the hope that it will be useful,
11* but WITHOUT ANY WARRANTY; without even the implied warranty of
12* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13* GNU General Public License for more details.
14*
15* You should have received a copy of the GNU General Public License
16* along with this program; if not, write to the Free Software
17* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18*/
19
20/* This code was originally generated using an i915tool program. It has been
21 * improved by hand.
22 */
23
24#include <stdint.h>
25#include <console/console.h>
26#include <delay.h>
27#include <drivers/intel/gma/i915.h>
28#include <arch/io.h>
29#include "mainboard.h"
30
31/* these variables will be removed when the proper support is finished in src/drivers/intel/gma/intel_dp.c */
32int index;
33u32 auxout;
34u8 auxin[20];
35u8 msg[32];
36
37/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
38void runio(struct intel_dp *dp);
39
40void runio(struct intel_dp *dp)
41{
42 u8 read_val;
43
44 intel_dp_wait_panel_power_control(0xabcd0008);
45
46 /* vbios spins at this point. Some haswell weirdness? */
47 intel_dp_wait_panel_power_control(0xabcd0008);
48
49 /* This should be a function like intel_panel_enable_backlight
50 However, we are not sure how the value 0x3a9 comes up.
51 It has to do something with PWM frequency */
52 gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
53 gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
54 gtt_write(BLC_PWM_PCH_CTL1,BLM_PCH_PWM_ENABLE);
55
56 gtt_write(DEIIR,0x00008000);
57 intel_dp_wait_reg(DEIIR, 0x00000000);
58
59 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
60
61 intel_dp_sink_dpms(dp, 0);
62
63 intel_dp_get_max_downspread(dp, &read_val);
64
65 intel_dp_set_m_n_regs(dp);
66
67 intel_dp_set_resolution(dp);
68
69 gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
70 gtt_write(PIPECONF(dp->transcoder),0x00000000);
71 gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
72
73 mainboard_set_port_clk_dp(dp);
74 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
75 gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
76 gtt_write(DEIIR,0x00000080);
77
78 gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
79 gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
80
81 intel_dp_wait_panel_power_control(0xabcd000a);
82
83 /* what is this doing? Not sure yet. */
84 intel_dp_i2c_write(dp, 0x0);
85 intel_dp_i2c_read(dp, &read_val);
86 intel_dp_i2c_write(dp, 0x04);
87 intel_dp_i2c_read(dp, &read_val);
88 intel_dp_i2c_write(dp, 0x7e);
89 intel_dp_i2c_read(dp, &read_val);
90
91 /* this needs to be a call to a function */
92 gtt_write(DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091);
93 gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
94 gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091);
95
96 /* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */
97 gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a);
98 gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a);
99
100 intel_dp_set_bw(dp);
101 intel_dp_set_lane_count(dp);
102
103 mainboard_train_link(dp);
104
105 /* need a function: intel_ddi_set_tp or similar */
106 gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_IDLE);
107 gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_NORMAL);
108
109 gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
110 gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
111 gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
112
113 /* some of this is not needed. */
114 gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
115
116 gtt_write(SDEIIR,0x00000000);
117 gtt_write(DEIIR,0x00000000);
118 gtt_write(DEIIR,0x00008000);
119 intel_dp_wait_reg(DEIIR, 0x00000000);
120
121 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
122 gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
123
124 gtt_write(DEIIR,0x00000080);
125 intel_dp_wait_reg(DEIIR, 0x00000000);
126
127 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
128 gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
129
130 gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON);
131
132 gtt_write(SDEIIR,0x00000000);
133 gtt_write(SDEIIR,0x00000000);
134 gtt_write(DEIIR,0x00000000);
135}