blob: f3316f4a47c8482d70b3b5db043b5fa1088f360b [file] [log] [blame]
Ronald G. Minnich2120e0e22013-10-09 15:53:43 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2013 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <types.h>
21#include <string.h>
22#include <stdlib.h>
23#include <device/device.h>
24#include <device/device.h>
25#include <device/pci_def.h>
26#include <device/pci_ops.h>
27#include <console/console.h>
28#include <delay.h>
29#include <pc80/mc146818rtc.h>
30#include <arch/acpi.h>
31#include <arch/io.h>
32#include <arch/interrupt.h>
33#include <boot/coreboot_tables.h>
34#include "hda_verb.h"
35#include <smbios.h>
36#include <device/pci.h>
37#include <ec/google/chromeec/ec.h>
38#include <cbfs_core.h>
39
40#include <cpu/x86/tsc.h>
41#include <cpu/x86/cache.h>
42#include <cpu/x86/mtrr.h>
43#include <cpu/x86/msr.h>
44#include <edid.h>
45#include <drivers/intel/gma/i915.h>
46#include "mainboard.h"
47
48/*
49 * Here is the rough outline of how we bring up the display:
50 * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
51 * 2. Source determines video mode by reading DPCD receiver capability field
52 * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
53 * 0000Dh).
54 * 3. Sink replies DPCD receiver capability field.
55 * 4. Source starts EDID read thru I2C-over-AUX.
56 * 5. Sink replies EDID thru I2C-over-AUX.
57 * 6. Source determines link configuration, such as MAX_LINK_RATE and
58 * MAX_LANE_COUNT. Source also determines which type of eDP Authentication
59 * method to use and writes DPCD link configuration field (DPCD 00100h to
60 * 0010Ah) including eDP configuration set (DPCD 0010Ah).
61 * 7. Source starts link training. Sink does clock recovery and equalization.
62 * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
63 * 9. Sink replies DPCD link status field. If main link is not stable, Source
64 * repeats Step 7.
65 * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
66 * parameters and recovers stream clock.
67 * 11. Source sends video data.
68 */
69
70/* how many bytes do we need for the framebuffer?
71 * Well, this gets messy. To get an exact answer, we have
72 * to ask the panel, but we'd rather zero the memory
73 * and set up the gtt while the panel powers up. So,
74 * we take a reasonable guess, secure in the knowledge that the
75 * MRC has to overestimate the number of bytes used.
76 * 8 MiB is a very safe guess. There may be a better way later, but
77 * fact is, the initial framebuffer is only very temporary. And taking
78 * a little long is ok; this is done much faster than the AUX
79 * channel is ready for IO.
80 */
81#define FRAME_BUFFER_BYTES (8*MiB)
82/* how many 4096-byte pages do we need for the framebuffer?
83 * There are hard ways to get this, and easy ways:
84 * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
85 * on this chip (and in fact every Intel graphics chip we've seen).
86 */
87#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
88
89static unsigned int *mmio;
90static unsigned int graphics;
91static unsigned int physbase;
92
93void ug1(int);
94void ug2(int);
95void ug22(int);
96void ug3(int);
97
98/* GTT is the Global Translation Table for the graphics pipeline.
99 * It is used to translate graphics addresses to physical
100 * memory addresses. As in the CPU, GTTs map 4K pages.
101 * The setgtt function adds a further bit of flexibility:
102 * it allows you to set a range (the first two parameters) to point
103 * to a physical address (third parameter);the physical address is
104 * incremented by a count (fourth parameter) for each GTT in the
105 * range.
106 * Why do it this way? For ultrafast startup,
107 * we can point all the GTT entries to point to one page,
108 * and set that page to 0s:
109 * memset(physbase, 0, 4096);
110 * setgtt(0, 4250, physbase, 0);
111 * this takes about 2 ms, and is a win because zeroing
112 * the page takes a up to 200 ms.
113 * This call sets the GTT to point to a linear range of pages
114 * starting at physbase.
115 */
116
117#define GTT_PTE_BASE (2 << 20)
118
119static void
120setgtt(int start, int end, unsigned long base, int inc)
121{
122 int i;
123
124 for(i = start; i < end; i++){
125 u32 word = base + i*inc;
126 /* note: we've confirmed by checking
127 * the values that mrc does no
128 * useful setup before we run this.
129 */
130 gtt_write(GTT_PTE_BASE + i * 4, word|1);
131 gtt_read(GTT_PTE_BASE + i * 4);
132 }
133}
134
135static int i915_init_done = 0;
136
137/* fill the palette. */
138static void palette(void)
139{
140 int i;
141 unsigned long color = 0;
142
143 for(i = 0; i < 256; i++, color += 0x010101){
144 gtt_write(_LGC_PALETTE_A + (i<<2),color);
145 }
146}
147
148void dp_init_dim_regs(struct intel_dp *dp);
149void dp_init_dim_regs(struct intel_dp *dp)
150{
151 struct edid *edid = &(dp->edid);
152
153 dp->bytes_per_pixel = edid->framebuffer_bits_per_pixel / 8;
154
155 dp->stride = edid->bytes_per_line;
156
157 dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
158
159 dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
160
161 dp->hsync = (edid->ha + edid->hso - 1) |
162 ((edid->ha + edid->hso + edid->hspw - 1) << 16);
163
164 dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
165
166 dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
167
168 dp->vsync = (edid->va + edid->vso - 1) |
169 ((edid->va + edid->vso + edid->vspw - 1) << 16);
170
171 /* PIPEASRC is wid-1 x ht-1 */
172 dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1);
173
174 dp->pfa_pos = 0;
175
176 dp->pfa_ctl = 0x80800000;
177
178 dp->pfa_sz = (edid->ha << 16) | (edid->va);
179
180 dp->flags = intel_ddi_calc_transcoder_flags(3 * 6, /* bits per color is 6 */
181 dp->port,
182 dp->pipe,
183 dp->type,
184 dp->lane_count,
185 dp->pfa_sz,
186 dp->edid.phsync == '+'?1:0,
187 dp->edid.pvsync == '+'?1:0);
188
189 dp->transcoder = intel_ddi_get_transcoder(dp->port,
190 dp->pipe);
191
192 intel_dp_compute_m_n(dp->pipe_bits_per_pixel,
193 dp->lane_count,
194 dp->edid.pixel_clock,
195 dp->edid.link_clock,
196 &dp->m_n);
197
198 printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride);
199 printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal);
200 printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank);
201 printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync);
202 printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal);
203 printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank);
204 printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync);
205 printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc);
206 printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
207 printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
208 printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz);
209 printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m);
210 printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n);
211 printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
212 printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m);
213 printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n);
214 printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
215}
216
217void mainboard_train_link(struct intel_dp *intel_dp)
218{
219 u8 read_val;
220 u8 link_status[DP_LINK_STATUS_SIZE];
221
222 gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
223 gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011);
224
225 intel_dp_get_training_pattern(intel_dp, &read_val);
226 intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
227 intel_dp_get_lane_count(intel_dp, &read_val);
228 intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
229 intel_dp_get_link_status(intel_dp, link_status);
230
231 gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
232
233 intel_dp_get_training_pattern(intel_dp, &read_val);
234 intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
235 intel_dp_get_link_status(intel_dp, link_status);
236 intel_dp_get_lane_align_status(intel_dp, &read_val);
237 intel_dp_get_training_pattern(intel_dp, &read_val);
238 intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
239}
240
241#define TEST_GFX 0
242
243#if TEST_GFX
244static void test_gfx(struct intel_dp *dp)
245{
246 int i;
247
248 /* This is a sanity test code which fills the screen with two bands --
249 green and blue. It is very useful to ensure all the initializations
250 are made right. Thus, to be used only for testing, not otherwise
251 */
252 for (i = 0; i < (dp->edid.va - 4); i++) {
253 u32 *l;
254 int j;
255 u32 tcolor = 0x0ff;
256 for (j = 0; j < (dp->edid.ha-4); j++) {
257 if (j == (dp->edid.ha/2)) {
258 tcolor = 0xff00;
259 }
260 l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor));
261 memcpy(l,&tcolor,sizeof(tcolor));
262 }
263 }
264}
265#else
266static void test_gfx(struct intel_dp *dp) {}
267#endif
268
269
270void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
271{
272 u32 ddi_pll_sel = 0;
273
274 switch (intel_dp->link_bw) {
275 case DP_LINK_BW_1_62:
276 ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
277 break;
278 case DP_LINK_BW_2_7:
279 ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
280 break;
281 case DP_LINK_BW_5_4:
282 ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
283 break;
284 default:
285 printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
286 return;
287 }
288
289 gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
290}
291
292int i915lightup(unsigned int pphysbase, unsigned int pmmio,
293 unsigned int pgfx, unsigned int init_fb)
294{
295 int must_cycle_power = 0;
296 struct intel_dp adp, *dp = &adp;
297 int i;
298 int edid_ok;
299 int pixels = FRAME_BUFFER_BYTES/64;
300
301 mmio = (void *)pmmio;
302 physbase = pphysbase;
303 graphics = pgfx;
304 printk(BIOS_SPEW,
305 "i915lightup: graphics %p mmio %p"
306 "physbase %08x\n",
307 (void *)graphics, mmio, physbase);
308
309 void runio(struct intel_dp *dp);
310 void runlinux(struct intel_dp *dp);
311 dp->gen = 8; // This is gen 8 which we believe is Haswell
312 dp->is_haswell = 1;
313 dp->DP = 0x2;
314 /* These values are used for training the link */
315 dp->lane_count = 2;
316 dp->link_bw = DP_LINK_BW_2_7;
317 dp->panel_power_down_delay = 600;
318 dp->panel_power_up_delay = 200;
319 dp->panel_power_cycle_delay = 600;
320 dp->pipe = PIPE_A;
321 dp->port = PORT_A;
322 dp->plane = PLANE_A;
323 dp->clock = 160000;
324 dp->pipe_bits_per_pixel = 32;
325 dp->type = INTEL_OUTPUT_EDP;
326 dp->output_reg = DP_A;
327 /* observed from YABEL. */
328 dp->aux_clock_divider = 0xe1;
329 dp->precharge = 3;
330
331 /* 1. Normal mode: Set the first page to zero and make
332 all GTT entries point to the same page
333 2. Developer/Recovery mode: We do not zero out all
334 the pages pointed to by GTT in order to avoid wasting time */
335 if (init_fb)
336 setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
337 else {
338 setgtt(0, FRAME_BUFFER_PAGES, physbase, 0);
339 memset((void*)graphics, 0, 4096);
340 }
341
342 dp->address = 0x50;
343
344 if ( !intel_dp_get_dpcd(dp) )
345 goto fail;
346
347 intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL);
348 for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){
349 if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ,
350 0x50, &dp->rawedid[i]) < 0)
351 break;
352 dp->edidlen++;
353 }
354
355 edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
356 printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
357
358 dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
359
360 printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",dp->edid.pixel_clock, dp->edid.link_clock);
361
362 dp_init_dim_regs(dp);
363
364 intel_ddi_set_pipe_settings(dp);
365
366 runio(dp);
367
368 palette();
369
370 pixels = dp->edid.ha * (dp->edid.va-4) * 4;
371 printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
372
373 test_gfx(dp);
374
375 set_vbe_mode_info_valid(&dp->edid, graphics);
376 i915_init_done = 1;
377 return i915_init_done;
378
379fail:
380 printk(BIOS_SPEW, "Graphics could not be started;");
381 if (0 && must_cycle_power){
382 printk(BIOS_SPEW, "Turn off power and wait ...");
383 gtt_write(PCH_PP_CONTROL,0xabcd0000);
384 udelay(600000);
385 gtt_write(PCH_PP_CONTROL,0xabcd000f);
386 }
387 printk(BIOS_SPEW, "Returning.\n");
388 return 0;
389}