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Katherine Hsieh674c0892017-03-09 17:18:50 +08001chip soc/intel/apollolake
2
3 device cpu_cluster 0 on
4 device lapic 0 on end
5 end
6
7 register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
8 # Disable unused clkreq of PCIe root ports
9 register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
10 register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
11 register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
12 register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
13 register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
14
15 # GPIO for PERST_0
16 # If the Board has PERST_0 signal, assign the GPIO
17 # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
18 register "prt0_gpio" = "GPIO_122"
19
20 # EMMC TX DATA Delay 1
21 # Refer to EDS-Vol2-22.3.
22 # [14:8] steps of delay for HS400, each 125ps.
23 # [6:0] steps of delay for SDR104/HS200, each 125ps.
24 register "emmc_tx_data_cntl1" = "0x0C16"
25
26 # EMMC TX DATA Delay 2
27 # Refer to EDS-Vol2-22.3.
28 # [30:24] steps of delay for SDR50, each 125ps.
29 # [22:16] steps of delay for DDR50, each 125ps.
30 # [14:8] steps of delay for SDR25/HS50, each 125ps.
31 # [6:0] steps of delay for SDR12, each 125ps.
32 register "emmc_tx_data_cntl2" = "0x28162828"
33
34 # EMMC RX CMD/DATA Delay 1
35 # Refer to EDS-Vol2-22.3.
36 # [30:24] steps of delay for SDR50, each 125ps.
37 # [22:16] steps of delay for DDR50, each 125ps.
38 # [14:8] steps of delay for SDR25/HS50, each 125ps.
39 # [6:0] steps of delay for SDR12, each 125ps.
40 register "emmc_rx_cmd_data_cntl1" = "0x00181717"
41
42 # EMMC RX CMD/DATA Delay 2
43 # Refer to EDS-Vol2-22.3.
44 # [17:16] stands for Rx Clock before Output Buffer
45 # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
46 # [6:0] steps of delay for HS200, each 125ps.
47 register "emmc_rx_cmd_data_cntl2" = "0x10008"
48
49 # Enable DPTF
50 register "dptf_enable" = "1"
51
52 # PL1 override 12000 mW: the energy calculation is wrong with the
53 # current VR solution. Experiments show that SoC TDP max (6W) can
54 # be reached when RAPL PL1 is set to 12W.
55 register "tdp_pl1_override_mw" = "12000"
56 # Set RAPL PL2 to 15W.
57 register "tdp_pl2_override_mw" = "15000"
58
59 # Enable Audio Clock and Power gating
60 register "hdaudio_clk_gate_enable" = "1"
61 register "hdaudio_pwr_gate_enable" = "1"
62 register "hdaudio_bios_config_lockdown" = "1"
63
64 # Enable lpss s0ix
65 register "lpss_s0ix_enable" = "1"
66
67 # GPE configuration
68 # Note that GPE events called out in ASL code rely on this
69 # route, i.e., if this route changes then the affected GPE
70 # offset bits also need to be changed. This sets the PMC register
71 # GPE_CFG fields.
72 register "gpe0_dw1" = "PMC_GPE_N_31_0"
73 register "gpe0_dw2" = "PMC_GPE_N_63_32"
74 register "gpe0_dw3" = "PMC_GPE_SW_31_0"
75
76 # Enable I2C0 for audio codec at 400kHz
77 register "i2c[0]" = "{
78 .speed = I2C_SPEED_FAST,
79 .rise_time_ns = 104,
80 .fall_time_ns = 52,
81 }"
82
83 # Enable I2C2 bus early for TPM at 400kHz
84 register "i2c[2]" = "{
85 .early_init = 1,
86 .speed = I2C_SPEED_FAST,
87 .rise_time_ns = 57,
88 .fall_time_ns = 28,
89 }"
90
91 # touchscreen at 400kHz
92 register "i2c[3]" = "{
93 .speed = I2C_SPEED_FAST,
94 .rise_time_ns = 76,
95 .fall_time_ns = 164,
96 }"
97
98 # trackpad at 400kHz
99 register "i2c[4]" = "{
100 .speed = I2C_SPEED_FAST,
101 .rise_time_ns = 114,
102 .fall_time_ns = 164,
103 }"
104
105 # digitizer at 400kHz
106 register "i2c[5]" = "{
107 .speed = I2C_SPEED_FAST,
108 .rise_time_ns = 152,
109 .fall_time_ns = 30,
110 }"
111
112 # Minimum SLP S3 assertion width 28ms.
113 register "slp_s3_assertion_width_usecs" = "28000"
114
Katherine Hsiehaef0d6b2018-02-27 20:23:53 +0800115 # Override USB2 PER PORT register (PORT 1)
116 register "usb2eye[1]" = "{
117 .Usb20PerPortPeTxiSet = 4,
118 .Usb20PerPortTxiSet = 4,
119 .Usb20IUsbTxEmphasisEn = 1,
120 .Usb20PerPortTxPeHalf = 0,
121 }"
122
123 # Override USB2 PER PORT register (PORT 4)
124 register "usb2eye[4]" = "{
125 .Usb20PerPortPeTxiSet = 7,
126 .Usb20PerPortTxiSet = 7,
127 .Usb20IUsbTxEmphasisEn = 1,
128 .Usb20PerPortTxPeHalf = 0,
129 }"
130
Katherine Hsieh674c0892017-03-09 17:18:50 +0800131 device domain 0 on
132 device pci 00.0 on end # - Host Bridge
133 device pci 00.1 on end # - DPTF
134 device pci 00.2 on end # - NPK
135 device pci 02.0 on end # - Gen
136 device pci 03.0 on end # - Iunit
137 device pci 0d.0 on end # - P2SB
138 device pci 0d.1 on end # - PMC
139 device pci 0d.2 on end # - SPI
140 device pci 0d.3 on end # - Shared SRAM
141 device pci 0e.0 on # - Audio
142 chip drivers/generic/max98357a
143 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
144 register "sdmode_delay" = "5"
145 device generic 0 on end
146 end
147 end
148 device pci 11.0 off end # - ISH
149 device pci 12.0 off end # - SATA
150 device pci 13.0 off end # - Root Port 2 - PCIe-A 0
151 device pci 13.1 off end # - Root Port 3 - PCIe-A 1
152 device pci 13.2 off end # - Root Port 4 - PCIe-A 2
153 device pci 13.3 off end # - Root Port 5 - PCIe-A 3
154 device pci 14.0 on
155 chip drivers/intel/wifi
156 register "wake" = "GPE0_DW3_00"
157 device pci 00.0 on end
158 end
159 end # - Root Port 0 - PCIe-B 0 - Wifi
160 device pci 14.1 off end # - Root Port 1 - PCIe-B 1
161 device pci 15.0 on end # - XHCI
162 device pci 15.1 off end # - XDCI
163 device pci 16.0 on # - I2C 0
164 chip drivers/i2c/da7219
165 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
166 register "btn_cfg" = "50"
167 register "mic_det_thr" = "500"
168 register "jack_ins_deb" = "20"
169 register "jack_det_rate" = ""32ms_64ms""
170 register "jack_rem_deb" = "1"
171 register "a_d_btn_thr" = "0xa"
172 register "d_b_btn_thr" = "0x16"
173 register "b_c_btn_thr" = "0x21"
174 register "c_mic_btn_thr" = "0x3e"
175 register "btn_avg" = "4"
176 register "adc_1bit_rpt" = "1"
177 register "micbias_lvl" = "2600"
178 register "mic_amp_in_sel" = ""diff""
179 device i2c 1a on end
180 end
181 end
182 device pci 16.1 on end # - I2C 1
183 device pci 16.2 on
184 chip drivers/i2c/tpm
185 register "hid" = ""GOOG0005""
186 register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
187 device i2c 50 on end
188 end
189 end # - I2C 2
190 device pci 16.3 on
191 chip drivers/i2c/generic
Katherine Hsiehb980d1a2017-03-13 14:37:49 +0800192 register "hid" = ""RAYD0001""
193 register "desc" = ""Raydium Touchscreen""
Katherine Hsieh674c0892017-03-09 17:18:50 +0800194 register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)"
195 register "probed" = "1"
196 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
197 register "reset_delay_ms" = "20"
198 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
199 register "enable_delay_ms" = "1"
200 register "has_power_resource" = "1"
Katherine Hsiehb980d1a2017-03-13 14:37:49 +0800201 device i2c 39 on end
Katherine Hsieh674c0892017-03-09 17:18:50 +0800202 end
203 end # - I2C 3
204 device pci 17.0 on
205 chip drivers/i2c/generic
206 register "hid" = ""ELAN0000""
207 register "desc" = ""ELAN Touchpad""
208 register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)"
209 register "wake" = "GPE0_DW1_15"
210 register "probed" = "1"
211 device i2c 15 on end
212 end
213 end # - I2C 4
214 device pci 17.1 on
215 chip drivers/i2c/hid
216 register "generic.hid" = ""WCOM50C1""
217 register "generic.desc" = ""WCOM Digitizer""
218 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"
219 register "hid_desc_reg_offset" = "0x1"
220 device i2c 0x9 on end
221 end
222 end # - I2C 5
223 device pci 17.2 off end # - I2C 6
224 device pci 17.3 off end # - I2C 7
225 device pci 18.0 on end # - UART 0
226 device pci 18.1 on end # - UART 1
227 device pci 18.2 on end # - UART 2
228 device pci 18.3 off end # - UART 3
229 device pci 19.0 on end # - SPI 0
230 device pci 19.1 off end # - SPI 1
231 device pci 19.2 off end # - SPI 2
232 device pci 1a.0 on end # - PWM
233 device pci 1b.0 on end # - SDCARD
234 device pci 1c.0 on end # - eMMC
235 device pci 1e.0 off end # - SDIO
236 device pci 1f.0 on # - LPC
237 chip ec/google/chromeec
238 device pnp 0c09.0 on end
239 end
240 end
241 device pci 1f.1 on end # - SMBUS
242 end
243end