blob: e08889ea77629314678ac5ab291836d836f0249a [file] [log] [blame]
Aaron Durbine065bb42016-05-10 15:09:44 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/acpi.h>
17#include <console/console.h>
Aaron Durbin91fa9d72016-09-23 16:38:27 -050018#include <ec/ec.h>
Aaron Durbine065bb42016-05-10 15:09:44 -050019#include <ec/google/chromeec/ec.h>
Ravi Sarawadiefa606b2017-08-04 16:26:09 -070020#include <intelblocks/lpc_lib.h>
Aaron Durbine065bb42016-05-10 15:09:44 -050021#include <rules.h>
Aaron Durbin114d7c32016-09-02 15:58:16 -050022#include <variant/ec.h>
Aaron Durbine065bb42016-05-10 15:09:44 -050023
Aaron Durbine065bb42016-05-10 15:09:44 -050024static void ramstage_ec_init(void)
25{
Furquan Shaikh2749c522017-10-04 14:01:41 -070026 const struct google_chromeec_event_info info = {
27 .log_events = MAINBOARD_EC_LOG_EVENTS,
28 .sci_events = MAINBOARD_EC_SCI_EVENTS,
29 .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
30 .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
Jenny TCb8d338c2017-10-27 17:44:20 +053031 .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
Furquan Shaikh2749c522017-10-04 14:01:41 -070032 };
33
Aaron Durbine065bb42016-05-10 15:09:44 -050034 printk(BIOS_ERR, "mainboard: EC init\n");
35
Furquan Shaikh2749c522017-10-04 14:01:41 -070036 google_chromeec_events_init(&info, acpi_is_wakeup_s3());
Aaron Durbine065bb42016-05-10 15:09:44 -050037}
38
39static void bootblock_ec_init(void)
40{
41 uint16_t ec_ioport_base;
42 size_t ec_ioport_size;
43
44 /*
Ravi Sarawadiefa606b2017-08-04 16:26:09 -070045 * Set up LPC decoding for the ChromeEC I/O port ranges:
46 * - Ports 62/66, 60/64, and 200->208
47 * - ChromeEC specific communication I/O ports.
48 */
49 lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
50 | LPC_IOE_LGE_200);
Aaron Durbine065bb42016-05-10 15:09:44 -050051 google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
52 lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
53}
54
55void mainboard_ec_init(void)
56{
57 if (ENV_RAMSTAGE)
58 ramstage_ec_init();
59 else if (ENV_BOOTBLOCK)
60 bootblock_ec_init();
61}