blob: dc634365556481789246754166eb1873a310f03c [file] [log] [blame]
Aaron Durbine065bb42016-05-10 15:09:44 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Aaron Durbinfec03282016-09-14 14:42:25 -050016#include <variant/ec.h>
17#include <variant/gpio.h>
18
Aaron Durbine065bb42016-05-10 15:09:44 -050019DefinitionBlock(
20 "dsdt.aml",
21 "DSDT",
22 0x05, // DSDT revision: ACPI v5.0
23 "COREv4", // OEM id
24 "COREBOOT", // OEM table id
25 0x20110725 // OEM revision
26)
27{
28 /* global NVS and variables */
Furquan Shaikh579fdb42016-06-13 22:29:00 -070029 #include <soc/intel/apollolake/acpi/globalnvs.asl>
Aaron Durbine065bb42016-05-10 15:09:44 -050030
Shaunak Sahaf6118c62016-06-03 17:11:12 -070031 /* CPU */
32 #include <soc/intel/apollolake/acpi/cpu.asl>
33
Aaron Durbine065bb42016-05-10 15:09:44 -050034 Scope (\_SB) {
35 Device (PCI0)
36 {
37 #include <soc/intel/apollolake/acpi/northbridge.asl>
38 #include <soc/intel/apollolake/acpi/southbridge.asl>
Saurabh Satijaaf9f35a2016-06-26 18:25:34 -070039 #include <soc/intel/apollolake/acpi/pch_hda.asl>
Aaron Durbine065bb42016-05-10 15:09:44 -050040 }
41 }
42
43 /* Chrome OS specific */
Aaron Durbine065bb42016-05-10 15:09:44 -050044 #include <vendorcode/google/chromeos/acpi/chromeos.asl>
45
46 /* Chipset specific sleep states */
47 #include <soc/intel/apollolake/acpi/sleepstates.asl>
48
Aaron Durbinfec03282016-09-14 14:42:25 -050049 /* Chrome OS Embedded Controller */
50 Scope (\_SB.PCI0.LPCB)
51 {
52 /* ACPI code for EC SuperIO functions */
53 #include <ec/google/chromeec/acpi/superio.asl>
54 /* ACPI code for EC functions */
55 #include <ec/google/chromeec/acpi/ec.asl>
56 }
57
58 /* Dynamic Platform Thermal Framework */
59 Scope (\_SB)
60 {
61 /* Per board variant specific definitions. */
62 #include <variant/acpi/dptf.asl>
63 /* Include soc specific DPTF changes */
64 #include <soc/intel/apollolake/acpi/dptf.asl>
65 /* Include common dptf ASL files */
66 #include <soc/intel/common/acpi/dptf/dptf.asl>
Shaunak Saha57f221e2016-07-12 16:03:29 -070067 }
Aaron Durbine065bb42016-05-10 15:09:44 -050068}