blob: 59ac217bbde2884e63d43589a65966229ed022be [file] [log] [blame]
Hannah Williams5e83e8b2018-02-09 18:35:17 -08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2018 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/acpi.h>
17#include <baseboard/variants.h>
18#include <cpu/x86/smm.h>
19#include <ec/google/chromeec/smm.h>
20#include <intelblocks/smihandler.h>
21#include <soc/pm.h>
22#include <soc/gpio.h>
23#include <variant/ec.h>
24#include <variant/gpio.h>
25
26void mainboard_smi_gpi_handler(const struct gpi_status *sts)
27{
28 if (gpi_status_get(sts, EC_SMI_GPI))
29 chromeec_smi_process_events();
30}
31
32void mainboard_smi_sleep(u8 slp_typ)
33{
34 const struct pad_config *pads;
35 size_t num;
36
37 pads = variant_sleep_gpio_table(&num);
38 gpio_configure_pads(pads, num);
39
40 chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
41 MAINBOARD_EC_S5_WAKE_EVENTS);
42}
43
44int mainboard_smi_apmc(u8 apmc)
45{
46 chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
47 MAINBOARD_EC_SMI_EVENTS);
48 return 0;
49}