blob: 8ed862c7bc54adf43710f893d9dabf97da56c614 [file] [log] [blame]
Hannah Williams5e83e8b2018-02-09 18:35:17 -08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2018 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/acpi.h>
17#include <arch/io.h>
18#include <console/console.h>
19#include <ec/ec.h>
20#include <ec/google/chromeec/ec.h>
21#include <intelblocks/lpc_lib.h>
22#include <rules.h>
23#include <variant/ec.h>
24
25static void ramstage_ec_init(void)
26{
27 static const struct google_chromeec_event_info info = {
28 .log_events = MAINBOARD_EC_LOG_EVENTS,
29 .sci_events = MAINBOARD_EC_SCI_EVENTS,
30 .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
31 .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
32 .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
33 };
34
35 printk(BIOS_ERR, "mainboard: EC init\n");
36
37 google_chromeec_events_init(&info, acpi_is_wakeup_s3());
38}
39
40static void bootblock_ec_init(void)
41{
42 uint16_t ec_ioport_base;
43 size_t ec_ioport_size;
44
45 /*
46 * Set up LPC decoding for the ChromeEC I/O port ranges:
47 * - Ports 62/66, 60/64, and 200->208
48 * - ChromeEC specific communication I/O ports.
49 */
50 lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
51 | LPC_IOE_LGE_200);
52 google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
53 lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
54}
55
56void mainboard_ec_init(void)
57{
58 if (ENV_RAMSTAGE)
59 ramstage_ec_init();
60 else if (ENV_BOOTBLOCK)
61 bootblock_ec_init();
62}