Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 15 | */ |
| 16 | |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 17 | #include <soc/intel/fsp_baytrail/include/soc/iomap.h> |
| 18 | #include <soc/intel/fsp_baytrail/include/soc/irq.h> |
| 19 | #include "../include/soc/baytrail.h" |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 20 | |
| 21 | Scope(\) |
| 22 | { |
| 23 | // IO-Trap at 0x800. This is the ACPI->SMI communication interface. |
| 24 | |
| 25 | OperationRegion(IO_T, SystemIO, 0x800, 0x10) |
| 26 | Field(IO_T, ByteAcc, NoLock, Preserve) |
| 27 | { |
| 28 | Offset(0x8), |
| 29 | TRP0, 8 // IO-Trap at 0x808 |
| 30 | } |
| 31 | |
| 32 | // Intel Legacy Block |
| 33 | OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) |
| 34 | Field (ILBS, AnyAcc, NoLock, Preserve) |
| 35 | { |
| 36 | Offset (0x8), |
| 37 | PRTA, 8, |
| 38 | PRTB, 8, |
| 39 | PRTC, 8, |
| 40 | PRTD, 8, |
| 41 | PRTE, 8, |
| 42 | PRTF, 8, |
| 43 | PRTG, 8, |
| 44 | PRTH, 8, |
| 45 | } |
| 46 | } |
| 47 | |
| 48 | Name(_HID,EISAID("PNP0A08")) // PCIe |
| 49 | Name(_CID,EISAID("PNP0A03")) // PCI |
| 50 | |
| 51 | Name(_ADR, 0) |
| 52 | Name(_BBN, 0) |
| 53 | |
Martin Roth | 91050b7 | 2014-11-16 21:41:35 -0700 | [diff] [blame] | 54 | Name (MCRS, ResourceTemplate() |
| 55 | { |
| 56 | // Bus Numbers |
| 57 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 58 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 59 | |
| 60 | // IO Region 0 |
| 61 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 62 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 63 | |
| 64 | // PCI Config Space |
| 65 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 66 | |
| 67 | // IO Region 1 |
| 68 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 69 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 70 | |
| 71 | // VGA memory (0xa0000-0xbffff) |
| 72 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 73 | Cacheable, ReadWrite, |
| 74 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 75 | 0x00020000,,, ASEG) |
| 76 | |
| 77 | // OPROM reserved (0xc0000-0xc3fff) |
| 78 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 79 | Cacheable, ReadWrite, |
| 80 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 81 | 0x00004000,,, OPR0) |
| 82 | |
| 83 | // OPROM reserved (0xc4000-0xc7fff) |
| 84 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 85 | Cacheable, ReadWrite, |
| 86 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 87 | 0x00004000,,, OPR1) |
| 88 | |
| 89 | // OPROM reserved (0xc8000-0xcbfff) |
| 90 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 91 | Cacheable, ReadWrite, |
| 92 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 93 | 0x00004000,,, OPR2) |
| 94 | |
| 95 | // OPROM reserved (0xcc000-0xcffff) |
| 96 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 97 | Cacheable, ReadWrite, |
| 98 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 99 | 0x00004000,,, OPR3) |
| 100 | |
| 101 | // OPROM reserved (0xd0000-0xd3fff) |
| 102 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 103 | Cacheable, ReadWrite, |
| 104 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 105 | 0x00004000,,, OPR4) |
| 106 | |
| 107 | // OPROM reserved (0xd4000-0xd7fff) |
| 108 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 109 | Cacheable, ReadWrite, |
| 110 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 111 | 0x00004000,,, OPR5) |
| 112 | |
| 113 | // OPROM reserved (0xd8000-0xdbfff) |
| 114 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 115 | Cacheable, ReadWrite, |
| 116 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 117 | 0x00004000,,, OPR6) |
| 118 | |
| 119 | // OPROM reserved (0xdc000-0xdffff) |
| 120 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 121 | Cacheable, ReadWrite, |
| 122 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 123 | 0x00004000,,, OPR7) |
| 124 | |
| 125 | // BIOS Extension (0xe0000-0xe3fff) |
| 126 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 127 | Cacheable, ReadWrite, |
| 128 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 129 | 0x00004000,,, ESG0) |
| 130 | |
| 131 | // BIOS Extension (0xe4000-0xe7fff) |
| 132 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 133 | Cacheable, ReadWrite, |
| 134 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 135 | 0x00004000,,, ESG1) |
| 136 | |
| 137 | // BIOS Extension (0xe8000-0xebfff) |
| 138 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 139 | Cacheable, ReadWrite, |
| 140 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 141 | 0x00004000,,, ESG2) |
| 142 | |
| 143 | // BIOS Extension (0xec000-0xeffff) |
| 144 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 145 | Cacheable, ReadWrite, |
| 146 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 147 | 0x00004000,,, ESG3) |
| 148 | |
| 149 | // System BIOS (0xf0000-0xfffff) |
| 150 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 151 | Cacheable, ReadWrite, |
| 152 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 153 | 0x00010000,,, FSEG) |
| 154 | |
Dave Frodin | 2eaa0d4 | 2015-04-23 06:04:46 -0600 | [diff] [blame] | 155 | // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) |
Martin Roth | 91050b7 | 2014-11-16 21:41:35 -0700 | [diff] [blame] | 156 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 157 | Cacheable, ReadWrite, |
Dave Frodin | 2eaa0d4 | 2015-04-23 06:04:46 -0600 | [diff] [blame] | 158 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 159 | 0x00000000,,, PMEM) |
Martin Roth | 91050b7 | 2014-11-16 21:41:35 -0700 | [diff] [blame] | 160 | |
| 161 | // TPM Area (0xfed40000-0xfed44fff) |
| 162 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 163 | Cacheable, ReadWrite, |
| 164 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 165 | 0x00005000,,, TPMR) |
Martin Roth | b95a074 | 2015-12-22 12:40:53 -0700 | [diff] [blame] | 166 | |
| 167 | // High PCI Memory Region |
| 168 | QwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 169 | Cacheable, ReadWrite, |
| 170 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 171 | 0x00000000,,, UMEM) |
Martin Roth | 91050b7 | 2014-11-16 21:41:35 -0700 | [diff] [blame] | 172 | }) |
| 173 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 174 | Method (_CRS, 0, Serialized) |
| 175 | { |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 176 | // Update PCI resource area |
Martin Roth | 91050b7 | 2014-11-16 21:41:35 -0700 | [diff] [blame] | 177 | CreateDwordField(MCRS, ^PMEM._MIN, PMIN) |
| 178 | CreateDwordField(MCRS, ^PMEM._MAX, PMAX) |
| 179 | CreateDwordField(MCRS, ^PMEM._LEN, PLEN) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 180 | |
| 181 | // TOLM is BMBOUND accessible from IOSF so is saved in NVS |
| 182 | Store (\TOLM, PMIN) |
Dave Frodin | 2eaa0d4 | 2015-04-23 06:04:46 -0600 | [diff] [blame] | 183 | Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 184 | Add (Subtract (PMAX, PMIN), 1, PLEN) |
| 185 | |
Martin Roth | b95a074 | 2015-12-22 12:40:53 -0700 | [diff] [blame] | 186 | // Update High PCI resource area |
| 187 | CreateQwordField(MCRS, ^UMEM._MIN, UMIN) |
| 188 | CreateQwordField(MCRS, ^UMEM._MAX, UMAX) |
| 189 | CreateQwordField(MCRS, ^UMEM._LEN, ULEN) |
| 190 | |
| 191 | Store(0x40000000 * 48, UMIN) // Set base address to 48GB |
| 192 | Store(0x40000000 * 16, ULEN) // Allocate 16GB for PCI space |
| 193 | Add(UMIN, Subtract(ULEN, 1), UMAX) |
| 194 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 195 | Return (MCRS) |
| 196 | } |
| 197 | |
| 198 | /* Device Resource Consumption */ |
| 199 | Device (PDRC) |
| 200 | { |
| 201 | Name (_HID, EISAID("PNP0C02")) |
| 202 | Name (_UID, 1) |
| 203 | |
| 204 | Name (PDRS, ResourceTemplate() { |
| 205 | Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) |
| 206 | Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) |
| 207 | Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) |
| 208 | Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) |
| 209 | Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) |
| 210 | Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) |
| 211 | Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) |
| 212 | Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) |
| 213 | }) |
| 214 | |
| 215 | // Current Resource Settings |
| 216 | Method (_CRS, 0, Serialized) |
| 217 | { |
| 218 | Return(PDRS) |
| 219 | } |
| 220 | } |
| 221 | |
| 222 | Method (_OSC, 4) |
| 223 | { |
| 224 | /* Check for proper GUID */ |
| 225 | If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) |
| 226 | { |
| 227 | /* Let OS control everything */ |
| 228 | Return (Arg3) |
| 229 | } |
| 230 | Else |
| 231 | { |
| 232 | /* Unrecognized UUID */ |
| 233 | CreateDWordField (Arg3, 0, CDW1) |
| 234 | Or (CDW1, 4, CDW1) |
| 235 | Return (Arg3) |
| 236 | } |
| 237 | } |
| 238 | |
| 239 | /* IOSF MBI Interface for kernel access */ |
| 240 | Device (IOSF) |
| 241 | { |
| 242 | Name (_HID, "INT33BD") |
| 243 | Name (_CID, "INT33BD") |
| 244 | Name (_UID, 1) |
| 245 | |
| 246 | Name (RBUF, ResourceTemplate () |
| 247 | { |
| 248 | /* MCR / MDR / MCRX */ |
| 249 | Memory32Fixed (ReadWrite, 0, 12, RBAR) |
| 250 | }) |
| 251 | |
| 252 | Method (_CRS) |
| 253 | { |
| 254 | CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) |
| 255 | Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS) |
| 256 | Return (^RBUF) |
| 257 | } |
| 258 | } |
| 259 | |
| 260 | // LPC Bridge 0:1f.0 |
| 261 | #include "lpc.asl" |
| 262 | |
| 263 | #if INCLUDE_EHCI |
| 264 | // USB EHCI 0:1d.0 |
| 265 | #include "usb.asl" |
| 266 | #endif |
| 267 | |
| 268 | #if INCLUDE_XHCI |
| 269 | // USB XHCI 0:14.0 |
| 270 | #include "xhci.asl" |
| 271 | #endif |
| 272 | |
| 273 | // IRQ routing for each PCI device |
| 274 | #include "irqroute.asl" |
| 275 | |
| 276 | Scope (\_SB) |
| 277 | { |
| 278 | // GPIO Devices |
| 279 | #include "gpio.asl" |
| 280 | |
| 281 | #if INCLUDE_LPSS |
| 282 | // LPSS Devices |
| 283 | #include "lpss.asl" |
| 284 | #endif |
| 285 | |
| 286 | #if INCLUDE_SCC |
| 287 | // SCC Devices |
| 288 | #include "scc.asl" |
| 289 | #endif |
| 290 | |
| 291 | #if INCLUDE_LPE |
| 292 | // LPE Device |
| 293 | #include "lpe.asl" |
| 294 | #endif |
| 295 | } |