Tobias Diedrich | d5e6618 | 2015-06-21 18:15:40 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
Tobias Diedrich | d5e6618 | 2015-06-21 18:15:40 +0200 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | /* |
| 15 | * Include this file into a mainboard DSDT inside the PCI device |
| 16 | * "Northbridge Miscellaneous Control (Northbridge function 3)" and it |
| 17 | * will expose the temperature sensor of the processor as a thermal |
| 18 | * zone. |
| 19 | * |
| 20 | * Families 10 through 14 and some family 15 CPUs are supported. |
| 21 | * |
| 22 | * If, for example, the NB Misc. Control device is on 0:18.3, include |
| 23 | * the following: |
| 24 | * |
| 25 | * Scope (\_SB.PCI0) { |
| 26 | * Device (K10M) { |
| 27 | * Name (_ADR, 0x00180003) |
| 28 | * #include <northbridge/amd/amdfam10/thermal_mixin.asl> |
| 29 | * } |
| 30 | * } |
| 31 | * |
| 32 | * Do not include this if the board is affected by erratum 319 as the |
| 33 | * thermal sensor of Socket F/AM2+ processors may be unreliable. |
| 34 | * (Erratum 319 affects AM2+ boards, AM3 and later should be fine) |
| 35 | */ |
| 36 | |
| 37 | #ifndef K10TEMP_HOT_OFFSET |
| 38 | # define K10TEMP_HOT_OFFSET 100 |
| 39 | #endif |
| 40 | |
| 41 | #define K10TEMP_KELVIN_OFFSET 2732 |
| 42 | #define K10TEMP_TLIMIT_OFFSET 520 |
| 43 | |
| 44 | OperationRegion (TCFG, PCI_Config, 0x64, 0x4) |
| 45 | Field (TCFG, ByteAcc, NoLock, Preserve) { |
| 46 | HTCE, 1, /* Hardware thermal control enable */ |
| 47 | , 15, |
| 48 | TLMT, 7, /* (LimitTmp - 52) / 0.5 */ |
| 49 | , 9, |
| 50 | } |
| 51 | |
| 52 | OperationRegion (TCTL, PCI_Config, 0xa4, 0x4) |
| 53 | Field (TCTL, ByteAcc, NoLock, Preserve) { |
| 54 | , 21, |
| 55 | TNOW, 11, /* CurTmp / 0.125 */ |
| 56 | } |
| 57 | |
| 58 | ThermalZone (TZ00) { |
| 59 | Name (_HID, EisaId ("PNP0C11")) |
| 60 | Name (_STR, Unicode ("AMD CPU Core Thermal Sensor")) |
| 61 | |
| 62 | Method (_STA) { |
| 63 | If (LEqual (HTCE, One)) { |
| 64 | Return (0x0F) |
| 65 | } |
| 66 | Return (Zero) |
| 67 | } |
| 68 | |
| 69 | Method (_TMP) { /* Current temp in tenths degree Kelvin. */ |
| 70 | Multiply (TNOW, 10, Local0) |
| 71 | ShiftRight (Local0, 3, Local0) |
| 72 | Return (Add (Local0, K10TEMP_KELVIN_OFFSET)) |
| 73 | } |
| 74 | |
| 75 | Method (_CRT) { /* Critical temp in tenths degree Kelvin. */ |
| 76 | Multiply (TLMT, 10, Local0) |
| 77 | ShiftRight (Local0, 1, Local0) |
| 78 | Add (Local0, K10TEMP_TLIMIT_OFFSET, Local0) |
| 79 | Return (Add (Local0, K10TEMP_KELVIN_OFFSET)) |
| 80 | } |
| 81 | |
| 82 | Method (_HOT) { /* Hot temp in tenths degree Kelvin. */ |
| 83 | Return (Subtract (_CRT, K10TEMP_HOT_OFFSET)) |
| 84 | } |
| 85 | } |