Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <string.h> |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 17 | #include <bootmode.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 18 | #include <arch/io.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 21 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 22 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 23 | #include <southbridge/intel/common/gpio.h> |
Aaron Durbin | b0f8151 | 2016-07-25 21:31:41 -0500 | [diff] [blame] | 24 | #include <vendorcode/google/chromeos/chromeos.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 25 | |
| 26 | #define GPIO_SPI_WP 24 |
| 27 | #define GPIO_REC_MODE 42 |
| 28 | #define GPIO_DEV_MODE 17 |
| 29 | |
| 30 | #define FLAG_SPI_WP 0 |
| 31 | #define FLAG_REC_MODE 1 |
| 32 | #define FLAG_DEV_MODE 2 |
| 33 | |
| 34 | #ifndef __PRE_RAM__ |
Stefan Reinauer | 3e4e303 | 2013-03-20 14:08:04 -0700 | [diff] [blame] | 35 | #include <boot/coreboot_tables.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 36 | #include "ec.h" |
| 37 | #include <ec/smsc/mec1308/ec.h> |
| 38 | |
Vadim Bendebury | 6b3d09e | 2012-08-28 14:37:57 -0700 | [diff] [blame] | 39 | #define GPIO_COUNT 6 |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 40 | |
| 41 | void fill_lb_gpios(struct lb_gpios *gpios) |
| 42 | { |
| 43 | device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); |
| 44 | u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); |
| 45 | u8 lid = ec_read(0x83); |
| 46 | |
| 47 | gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); |
| 48 | gpios->count = GPIO_COUNT; |
| 49 | |
| 50 | /* Write Protect: GPIO24 = KBC3_SPI_WP# */ |
| 51 | gpios->gpios[0].port = GPIO_SPI_WP; |
| 52 | gpios->gpios[0].polarity = ACTIVE_HIGH; |
Patrick Georgi | 961e8a4 | 2015-06-30 12:49:50 +0200 | [diff] [blame] | 53 | gpios->gpios[0].value = get_write_protect_state(); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 54 | strncpy((char *)gpios->gpios[0].name,"write protect", |
| 55 | GPIO_MAX_NAME_LENGTH); |
| 56 | |
| 57 | /* Recovery: GPIO42 = CHP3_REC_MODE# */ |
| 58 | gpios->gpios[1].port = GPIO_REC_MODE; |
| 59 | gpios->gpios[1].polarity = ACTIVE_LOW; |
| 60 | gpios->gpios[1].value = !get_recovery_mode_switch(); |
| 61 | strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); |
| 62 | |
| 63 | /* Developer: GPIO17 = KBC3_DVP_MODE */ |
| 64 | gpios->gpios[2].port = GPIO_DEV_MODE; |
| 65 | gpios->gpios[2].polarity = ACTIVE_HIGH; |
| 66 | gpios->gpios[2].value = get_developer_mode_switch(); |
| 67 | strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); |
| 68 | |
| 69 | gpios->gpios[3].port = 100; |
| 70 | gpios->gpios[3].polarity = ACTIVE_HIGH; |
| 71 | gpios->gpios[3].value = lid & 1; |
| 72 | strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); |
| 73 | |
| 74 | /* Power Button */ |
| 75 | gpios->gpios[4].port = 101; |
| 76 | gpios->gpios[4].polarity = ACTIVE_LOW; |
| 77 | gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1; |
| 78 | strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); |
Vadim Bendebury | 6b3d09e | 2012-08-28 14:37:57 -0700 | [diff] [blame] | 79 | |
| 80 | /* Did we load the VGA Option ROM? */ |
| 81 | gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ |
| 82 | gpios->gpios[5].polarity = ACTIVE_HIGH; |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 83 | gpios->gpios[5].value = gfx_get_init_done(); |
Vadim Bendebury | 6b3d09e | 2012-08-28 14:37:57 -0700 | [diff] [blame] | 84 | strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 85 | } |
| 86 | #endif |
| 87 | |
Patrick Georgi | 961e8a4 | 2015-06-30 12:49:50 +0200 | [diff] [blame] | 88 | int get_write_protect_state(void) |
| 89 | { |
| 90 | device_t dev; |
| 91 | #ifdef __PRE_RAM__ |
| 92 | dev = PCI_DEV(0, 0x1f, 2); |
| 93 | #else |
| 94 | dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); |
| 95 | #endif |
| 96 | return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; |
| 97 | } |
| 98 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 99 | int get_developer_mode_switch(void) |
| 100 | { |
| 101 | device_t dev; |
| 102 | #ifdef __PRE_RAM__ |
| 103 | dev = PCI_DEV(0, 0x1f, 2); |
| 104 | #else |
| 105 | dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); |
| 106 | #endif |
| 107 | return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1; |
| 108 | } |
| 109 | |
| 110 | int get_recovery_mode_switch(void) |
| 111 | { |
| 112 | device_t dev; |
| 113 | #ifdef __PRE_RAM__ |
| 114 | dev = PCI_DEV(0, 0x1f, 2); |
| 115 | #else |
| 116 | dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); |
| 117 | #endif |
| 118 | return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; |
| 119 | } |
| 120 | |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 121 | void init_bootmode_straps(void) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 122 | { |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 123 | #ifdef __PRE_RAM__ |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 124 | u32 flags = 0; |
| 125 | |
| 126 | /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 127 | if (get_gpio(GPIO_SPI_WP)) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 128 | flags |= (1 << FLAG_SPI_WP); |
| 129 | /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 130 | if (!get_gpio(GPIO_REC_MODE)) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 131 | flags |= (1 << FLAG_REC_MODE); |
| 132 | /* Developer: GPIO17 = KBC3_DVP_MODE, active high */ |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 133 | if (get_gpio(GPIO_DEV_MODE)) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 134 | flags |= (1 << FLAG_DEV_MODE); |
| 135 | |
| 136 | pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 137 | #endif |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 138 | } |
Aaron Durbin | b0f8151 | 2016-07-25 21:31:41 -0500 | [diff] [blame] | 139 | |
| 140 | static const struct cros_gpio cros_gpios[] = { |
| 141 | CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), |
| 142 | CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME), |
| 143 | CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), |
| 144 | }; |
| 145 | |
| 146 | void mainboard_chromeos_acpi_generate(void) |
| 147 | { |
| 148 | chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); |
| 149 | } |