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review.coreboot.org / coreboot / 1e24bf3f719f82c16fd577e87900e1aa0fd6605b / . / src / mainboard / roda / rv11 / gpio.c
blob: 54930d082ef33cf054ba0f420bd5a5dbb551ca59 [file] [log] [blame]
Dennis Wassenbergbd105162015-09-10 12:20:58 +0200[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015 secunet Security Networks AG
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <southbridge/intel/common/gpio.h>
17
18/*
19 * TODO: Investigate somehow... Current values are taken from a running
20 * system with vendor supplied firmware.
21 */
22static const struct pch_gpio_set1 pch_gpio_set1_mode = {
23 .gpio0 = GPIO_MODE_GPIO, /* strap */
24 .gpio1 = GPIO_MODE_GPIO, /* EC SMI# */
25 .gpio2 = GPIO_MODE_GPIO, /* strap */
26 .gpio3 = GPIO_MODE_GPIO, /* strapped weak high */
27 .gpio4 = GPIO_MODE_GPIO, /* DDR3 thermal ALERT# */
28 .gpio5 = GPIO_MODE_GPIO, /* DDR3 thermal THERM# */
29 .gpio6 = GPIO_MODE_GPIO, /* DGPU hotplug? */
30 .gpio7 = GPIO_MODE_GPIO, /* EC SCI# */
31 .gpio8 = GPIO_MODE_GPIO, /* strap */
32 .gpio9 = GPIO_MODE_NATIVE, /* USB OC #5 */
33 .gpio10 = GPIO_MODE_NATIVE, /* USB OC #6; strapped weak high */
34 .gpio11 = GPIO_MODE_GPIO, /* strapped weak high */
35 .gpio12 = GPIO_MODE_NATIVE, /* LAN PHY Power Control */
36 .gpio13 = GPIO_MODE_NATIVE, /* HDA Audio Dock Reset */
37 .gpio14 = GPIO_MODE_GPIO, /* EC wake SCI# */
38 .gpio15 = GPIO_MODE_GPIO, /* strapped high */
39 .gpio16 = GPIO_MODE_NATIVE, /* SATA 4 GP */
40 .gpio17 = GPIO_MODE_GPIO, /* strapped weak low */
41 .gpio18 = GPIO_MODE_NATIVE, /* PCIe clock request 1 */
42 .gpio19 = GPIO_MODE_NATIVE, /* SATA 9 GP */
43 .gpio20 = GPIO_MODE_NATIVE, /* PCIe clock request 2 */
44 .gpio21 = GPIO_MODE_NATIVE, /* SATA 0 GP */
45 .gpio22 = GPIO_MODE_GPIO, /* strap */
46 .gpio23 = GPIO_MODE_NATIVE, /* LPC DMA request 1; strapped weak high */
47 .gpio24 = GPIO_MODE_GPIO, /* strapped weak high */
48 .gpio25 = GPIO_MODE_NATIVE, /* PCIe clock request 3 */
49 .gpio26 = GPIO_MODE_NATIVE, /* PCIe clock request 4 */
50 .gpio27 = GPIO_MODE_GPIO, /* SATA power (active low) */
51 .gpio28 = GPIO_MODE_GPIO, /* PCH strap ODVR, Output LOW */
52 .gpio29 = GPIO_MODE_GPIO, /* Sleep LAN power (sleep low) */
53 .gpio30 = GPIO_MODE_NATIVE, /* Suspend Warning */
54 .gpio31 = GPIO_MODE_NATIVE, /* AC present */
55};
56
57static const struct pch_gpio_set1 pch_gpio_set1_direction = {
58 .gpio0 = GPIO_DIR_INPUT, /* Unknown Input */
59 .gpio1 = GPIO_DIR_INPUT, /* Unknown Input */
60 .gpio2 = GPIO_DIR_INPUT, /* Unknown Input */
61 .gpio3 = GPIO_DIR_INPUT, /* Unknown Input */
62 .gpio4 = GPIO_DIR_INPUT, /* Unknown Input */
63 .gpio5 = GPIO_DIR_INPUT, /* Unknown Input */
64 .gpio6 = GPIO_DIR_INPUT, /* Unknown Input */
65 .gpio7 = GPIO_DIR_INPUT, /* Unknown Input */
66 .gpio8 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
67 .gpio9 = GPIO_DIR_INPUT, /* Native */
68 .gpio10 = GPIO_DIR_INPUT, /* Native */
69 .gpio11 = GPIO_DIR_INPUT, /* Unknown Input */
70 .gpio12 = GPIO_DIR_INPUT, /* Native */
71 .gpio13 = GPIO_DIR_INPUT, /* Native */
72 .gpio14 = GPIO_DIR_INPUT, /* Unknown Input */
73 .gpio15 = GPIO_DIR_INPUT, /* Unknown Input */
74 .gpio16 = GPIO_DIR_INPUT, /* Native */
75 .gpio17 = GPIO_DIR_INPUT, /* Unknown Input */
76 .gpio18 = GPIO_DIR_INPUT, /* Native */
77 .gpio19 = GPIO_DIR_INPUT, /* Native */
78 .gpio20 = GPIO_DIR_INPUT, /* Native */
79 .gpio21 = GPIO_DIR_INPUT, /* Native */
80 .gpio22 = GPIO_DIR_INPUT, /* Unknown Input */
81 .gpio23 = GPIO_DIR_INPUT, /* Native */
82 .gpio24 = GPIO_DIR_INPUT, /* Unknown Input */
83 .gpio25 = GPIO_DIR_INPUT, /* Native */
84 .gpio26 = GPIO_DIR_INPUT, /* Native */
85 .gpio27 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
86 .gpio28 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
87 .gpio29 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
88 .gpio30 = GPIO_DIR_INPUT, /* Native */
89 .gpio31 = GPIO_DIR_INPUT, /* Native */
90};
91
92static const struct pch_gpio_set1 pch_gpio_set1_level = {
93 .gpio0 = GPIO_LEVEL_LOW, /* Unknown Input */
94 .gpio1 = GPIO_LEVEL_LOW, /* Unknown Input */
95 .gpio2 = GPIO_LEVEL_LOW, /* Unknown Input */
96 .gpio3 = GPIO_LEVEL_LOW, /* Unknown Input */
97 .gpio4 = GPIO_LEVEL_LOW, /* Unknown Input */
98 .gpio5 = GPIO_LEVEL_LOW, /* Unknown Input */
99 .gpio6 = GPIO_LEVEL_LOW, /* Unknown Input */
100 .gpio7 = GPIO_LEVEL_LOW, /* Unknown Input */
101 .gpio8 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
102 .gpio9 = GPIO_LEVEL_LOW, /* Native */
103 .gpio10 = GPIO_LEVEL_LOW, /* Native */
104 .gpio11 = GPIO_LEVEL_LOW, /* Unknown Input */
105 .gpio12 = GPIO_LEVEL_LOW, /* Native */
106 .gpio13 = GPIO_LEVEL_LOW, /* Native */
107 .gpio14 = GPIO_LEVEL_LOW, /* Unknown Input */
108 .gpio15 = GPIO_LEVEL_LOW, /* Unknown Input */
109 .gpio16 = GPIO_LEVEL_LOW, /* Native */
110 .gpio17 = GPIO_LEVEL_LOW, /* Unknown Input */
111 .gpio18 = GPIO_LEVEL_LOW, /* Native */
112 .gpio19 = GPIO_LEVEL_LOW, /* Native */
113 .gpio20 = GPIO_LEVEL_LOW, /* Native */
114 .gpio21 = GPIO_LEVEL_LOW, /* Native */
115 .gpio22 = GPIO_LEVEL_LOW, /* Unknown Input */
116 .gpio23 = GPIO_LEVEL_LOW, /* Native */
117 .gpio24 = GPIO_LEVEL_LOW, /* Unknown Input */
118 .gpio25 = GPIO_LEVEL_LOW, /* Native */
119 .gpio26 = GPIO_LEVEL_LOW, /* Native */
120 .gpio27 = GPIO_LEVEL_LOW, /* Unknown Output LOW */
121 .gpio28 = GPIO_LEVEL_LOW, /* Unknown Output LOW */
122 .gpio29 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
123 .gpio30 = GPIO_LEVEL_LOW, /* Native */
124 .gpio31 = GPIO_LEVEL_LOW, /* Native */
125};
126
127static const struct pch_gpio_set1 pch_gpio_set1_reset = {
128 .gpio0 = GPIO_RESET_PWROK,
129 .gpio1 = GPIO_RESET_PWROK,
130 .gpio2 = GPIO_RESET_PWROK,
131 .gpio3 = GPIO_RESET_PWROK,
132 .gpio4 = GPIO_RESET_PWROK,
133 .gpio5 = GPIO_RESET_PWROK,
134 .gpio6 = GPIO_RESET_PWROK,
135 .gpio7 = GPIO_RESET_PWROK,
136 .gpio8 = GPIO_RESET_PWROK,
137 .gpio9 = GPIO_RESET_PWROK,
138 .gpio10 = GPIO_RESET_PWROK,
139 .gpio11 = GPIO_RESET_PWROK,
140 .gpio12 = GPIO_RESET_PWROK,
141 .gpio13 = GPIO_RESET_PWROK,
142 .gpio14 = GPIO_RESET_PWROK,
143 .gpio15 = GPIO_RESET_PWROK,
144 .gpio16 = GPIO_RESET_PWROK,
145 .gpio17 = GPIO_RESET_PWROK,
146 .gpio18 = GPIO_RESET_PWROK,
147 .gpio19 = GPIO_RESET_PWROK,
148 .gpio20 = GPIO_RESET_PWROK,
149 .gpio21 = GPIO_RESET_PWROK,
150 .gpio22 = GPIO_RESET_PWROK,
151 .gpio23 = GPIO_RESET_PWROK,
152 .gpio24 = GPIO_RESET_PWROK,
153 .gpio25 = GPIO_RESET_PWROK,
154 .gpio26 = GPIO_RESET_PWROK,
155 .gpio27 = GPIO_RESET_PWROK,
156 .gpio28 = GPIO_RESET_PWROK,
157 .gpio29 = GPIO_RESET_PWROK,
158 .gpio30 = GPIO_RESET_RSMRST,
159 .gpio31 = GPIO_RESET_PWROK,
160};
161
162static const struct pch_gpio_set1 pch_gpio_set1_invert = {
163 .gpio0 = GPIO_NO_INVERT,
164 .gpio1 = GPIO_INVERT,
165 .gpio2 = GPIO_NO_INVERT,
166 .gpio3 = GPIO_INVERT,
167 .gpio4 = GPIO_NO_INVERT,
168 .gpio5 = GPIO_NO_INVERT,
169 .gpio6 = GPIO_NO_INVERT,
170 .gpio7 = GPIO_INVERT,
171 .gpio8 = GPIO_NO_INVERT,
172 .gpio9 = GPIO_NO_INVERT,
173 .gpio10 = GPIO_NO_INVERT,
174 .gpio11 = GPIO_NO_INVERT,
175 .gpio12 = GPIO_NO_INVERT,
176 .gpio13 = GPIO_NO_INVERT,
177 .gpio14 = GPIO_INVERT,
178 .gpio15 = GPIO_INVERT,
179 .gpio16 = GPIO_NO_INVERT,
180 .gpio17 = GPIO_NO_INVERT,
181 .gpio18 = GPIO_NO_INVERT,
182 .gpio19 = GPIO_NO_INVERT,
183 .gpio20 = GPIO_NO_INVERT,
184 .gpio21 = GPIO_NO_INVERT,
185 .gpio22 = GPIO_NO_INVERT,
186 .gpio23 = GPIO_NO_INVERT,
187 .gpio24 = GPIO_NO_INVERT,
188 .gpio25 = GPIO_NO_INVERT,
189 .gpio26 = GPIO_NO_INVERT,
190 .gpio27 = GPIO_NO_INVERT,
191 .gpio28 = GPIO_NO_INVERT,
192 .gpio29 = GPIO_NO_INVERT,
193 .gpio30 = GPIO_NO_INVERT,
194 .gpio31 = GPIO_NO_INVERT,
195};
196
197static const struct pch_gpio_set1 pch_gpio_set1_blink = {
198 .gpio0 = GPIO_NO_BLINK,
199 .gpio1 = GPIO_NO_BLINK,
200 .gpio2 = GPIO_NO_BLINK,
201 .gpio3 = GPIO_NO_BLINK,
202 .gpio4 = GPIO_NO_BLINK,
203 .gpio5 = GPIO_NO_BLINK,
204 .gpio6 = GPIO_NO_BLINK,
205 .gpio7 = GPIO_NO_BLINK,
206 .gpio8 = GPIO_NO_BLINK,
207 .gpio9 = GPIO_NO_BLINK,
208 .gpio10 = GPIO_NO_BLINK,
209 .gpio11 = GPIO_NO_BLINK,
210 .gpio12 = GPIO_NO_BLINK,
211 .gpio13 = GPIO_NO_BLINK,
212 .gpio14 = GPIO_NO_BLINK,
213 .gpio15 = GPIO_NO_BLINK,
214 .gpio16 = GPIO_NO_BLINK,
215 .gpio17 = GPIO_NO_BLINK,
216 .gpio18 = GPIO_NO_BLINK,
217 .gpio19 = GPIO_NO_BLINK,
218 .gpio20 = GPIO_NO_BLINK,
219 .gpio21 = GPIO_NO_BLINK,
220 .gpio22 = GPIO_NO_BLINK,
221 .gpio23 = GPIO_NO_BLINK,
222 .gpio24 = GPIO_NO_BLINK,
223 .gpio25 = GPIO_NO_BLINK,
224 .gpio26 = GPIO_NO_BLINK,
225 .gpio27 = GPIO_NO_BLINK,
226 .gpio28 = GPIO_NO_BLINK,
227 .gpio29 = GPIO_NO_BLINK,
228 .gpio30 = GPIO_NO_BLINK,
229 .gpio31 = GPIO_NO_BLINK,
230};
231
232static const struct pch_gpio_set2 pch_gpio_set2_mode = {
233 .gpio32 = GPIO_MODE_NATIVE, /* Native */
234 .gpio33 = GPIO_MODE_NATIVE, /* Native */
235 .gpio34 = GPIO_MODE_GPIO, /* Unknown Output LOW */
236 .gpio35 = GPIO_MODE_NATIVE, /* Native */
237 .gpio36 = GPIO_MODE_NATIVE, /* Native */
238 .gpio37 = GPIO_MODE_GPIO, /* Unknown Output LOW */
239 .gpio38 = GPIO_MODE_GPIO, /* Unknown Input */
240 .gpio39 = GPIO_MODE_GPIO, /* Unknown Input */
241 .gpio40 = GPIO_MODE_NATIVE, /* USB OC #1 */
242 .gpio41 = GPIO_MODE_NATIVE, /* USB OC #2 */
243 .gpio42 = GPIO_MODE_NATIVE, /* USB OC #3 */
244 .gpio43 = GPIO_MODE_NATIVE, /* USB OC #4 */
245 .gpio44 = GPIO_MODE_NATIVE, /* Native */
246 .gpio45 = GPIO_MODE_NATIVE, /* Native */
247 .gpio46 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
248 .gpio47 = GPIO_MODE_NATIVE, /* Native */
249 .gpio48 = GPIO_MODE_GPIO, /* Unknown Input */
250 .gpio49 = GPIO_MODE_GPIO, /* Unknown Input */
251 .gpio50 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
252 .gpio51 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
253 .gpio52 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
254 .gpio53 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
255 .gpio54 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
256 .gpio55 = GPIO_MODE_GPIO, /* Unknown Output LOW */
257 .gpio56 = GPIO_MODE_NATIVE, /* Native */
258 .gpio57 = GPIO_MODE_GPIO, /* Unknown Input */
259 .gpio58 = GPIO_MODE_NATIVE, /* Native */
260 .gpio59 = GPIO_MODE_NATIVE, /* USB OC #0 */
261 .gpio60 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
262 .gpio61 = GPIO_MODE_NATIVE, /* Native */
263 .gpio62 = GPIO_MODE_NATIVE, /* Native */
264 .gpio63 = GPIO_MODE_NATIVE, /* Native */
265};
266
267static const struct pch_gpio_set2 pch_gpio_set2_direction = {
268 .gpio32 = GPIO_DIR_INPUT, /* Native */
269 .gpio33 = GPIO_DIR_INPUT, /* Native */
270 .gpio34 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
271 .gpio35 = GPIO_DIR_INPUT, /* Native */
272 .gpio36 = GPIO_DIR_INPUT, /* Native */
273 .gpio37 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
274 .gpio38 = GPIO_DIR_INPUT, /* Unknown Input */
275 .gpio39 = GPIO_DIR_INPUT, /* Unknown Input */
276 .gpio40 = GPIO_DIR_INPUT, /* Native */
277 .gpio41 = GPIO_DIR_INPUT, /* Native */
278 .gpio42 = GPIO_DIR_INPUT, /* Native */
279 .gpio43 = GPIO_DIR_INPUT, /* Native */
280 .gpio44 = GPIO_DIR_INPUT, /* Native */
281 .gpio45 = GPIO_DIR_INPUT, /* Native */
282 .gpio46 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
283 .gpio47 = GPIO_DIR_INPUT, /* Native */
284 .gpio48 = GPIO_DIR_INPUT, /* Unknown Input */
285 .gpio49 = GPIO_DIR_INPUT, /* Unknown Input */
286 .gpio50 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
287 .gpio51 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
288 .gpio52 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
289 .gpio53 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
290 .gpio54 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
291 .gpio55 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
292 .gpio56 = GPIO_DIR_INPUT, /* Native */
293 .gpio57 = GPIO_DIR_INPUT, /* Unknown Input */
294 .gpio58 = GPIO_DIR_INPUT, /* Native */
295 .gpio59 = GPIO_DIR_INPUT, /* Native */
296 .gpio60 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
297 .gpio61 = GPIO_DIR_INPUT, /* Native */
298 .gpio62 = GPIO_DIR_INPUT, /* Native */
299 .gpio63 = GPIO_DIR_INPUT, /* Native */
300};
301
302static const struct pch_gpio_set2 pch_gpio_set2_level = {
303 .gpio32 = GPIO_LEVEL_LOW, /* Native */
304 .gpio33 = GPIO_LEVEL_LOW, /* Native */
305 .gpio34 = GPIO_LEVEL_LOW, /* Unknown Output LOW */
306 .gpio35 = GPIO_LEVEL_LOW, /* Native */
307 .gpio36 = GPIO_LEVEL_LOW, /* Native */
308 .gpio37 = GPIO_LEVEL_LOW, /* Unknown Output LOW */
309 .gpio38 = GPIO_LEVEL_LOW, /* Unknown Input */
310 .gpio39 = GPIO_LEVEL_LOW, /* Unknown Input */
311 .gpio40 = GPIO_LEVEL_LOW, /* Native */
312 .gpio41 = GPIO_LEVEL_LOW, /* Native */
313 .gpio42 = GPIO_LEVEL_LOW, /* Native */
314 .gpio43 = GPIO_LEVEL_LOW, /* Native */
315 .gpio44 = GPIO_LEVEL_LOW, /* Native */
316 .gpio45 = GPIO_LEVEL_LOW, /* Native */
317 .gpio46 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
318 .gpio47 = GPIO_LEVEL_LOW, /* Native */
319 .gpio48 = GPIO_LEVEL_LOW, /* Unknown Input */
320 .gpio49 = GPIO_LEVEL_LOW, /* Unknown Input */
321 .gpio50 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
322 .gpio51 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
323 .gpio52 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
324 .gpio53 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
325 .gpio54 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
326 .gpio55 = GPIO_LEVEL_LOW, /* Unknown Output LOW */
327 .gpio56 = GPIO_LEVEL_LOW, /* Native */
328 .gpio57 = GPIO_LEVEL_LOW, /* Unknown Input */
329 .gpio58 = GPIO_LEVEL_LOW, /* Native */
330 .gpio59 = GPIO_LEVEL_LOW, /* Native */
331 .gpio60 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
332 .gpio61 = GPIO_LEVEL_LOW, /* Native */
333 .gpio62 = GPIO_LEVEL_LOW, /* Native */
334 .gpio63 = GPIO_LEVEL_LOW, /* Native */
335};
336
337static const struct pch_gpio_set2 pch_gpio_set2_reset = {
338 .gpio32 = GPIO_RESET_PWROK,
339 .gpio33 = GPIO_RESET_PWROK,
340 .gpio34 = GPIO_RESET_PWROK,
341 .gpio35 = GPIO_RESET_PWROK,
342 .gpio36 = GPIO_RESET_PWROK,
343 .gpio37 = GPIO_RESET_PWROK,
344 .gpio38 = GPIO_RESET_PWROK,
345 .gpio39 = GPIO_RESET_PWROK,
346 .gpio40 = GPIO_RESET_PWROK,
347 .gpio41 = GPIO_RESET_PWROK,
348 .gpio42 = GPIO_RESET_PWROK,
349 .gpio43 = GPIO_RESET_PWROK,
350 .gpio44 = GPIO_RESET_PWROK,
351 .gpio45 = GPIO_RESET_PWROK,
352 .gpio46 = GPIO_RESET_PWROK,
353 .gpio47 = GPIO_RESET_PWROK,
354 .gpio48 = GPIO_RESET_PWROK,
355 .gpio49 = GPIO_RESET_PWROK,
356 .gpio50 = GPIO_RESET_PWROK,
357 .gpio51 = GPIO_RESET_PWROK,
358 .gpio52 = GPIO_RESET_PWROK,
359 .gpio53 = GPIO_RESET_PWROK,
360 .gpio54 = GPIO_RESET_PWROK,
361 .gpio55 = GPIO_RESET_PWROK,
362 .gpio56 = GPIO_RESET_PWROK,
363 .gpio57 = GPIO_RESET_PWROK,
364 .gpio58 = GPIO_RESET_PWROK,
365 .gpio59 = GPIO_RESET_PWROK,
366 .gpio60 = GPIO_RESET_PWROK,
367 .gpio61 = GPIO_RESET_PWROK,
368 .gpio62 = GPIO_RESET_PWROK,
369 .gpio63 = GPIO_RESET_PWROK,
370};
371
372static const struct pch_gpio_set3 pch_gpio_set3_mode = {
373 .gpio64 = GPIO_MODE_NATIVE, /* Native */
374 .gpio65 = GPIO_MODE_NATIVE, /* Native */
375 .gpio66 = GPIO_MODE_GPIO, /* Unknown Output LOW */
376 .gpio67 = GPIO_MODE_GPIO, /* Unknown Input */
377 .gpio68 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
378 .gpio69 = GPIO_MODE_GPIO, /* Unknown Input */
379 .gpio70 = GPIO_MODE_NATIVE, /* Native */
380 .gpio71 = GPIO_MODE_NATIVE, /* Native */
381 .gpio72 = GPIO_MODE_NATIVE, /* Native */
382 .gpio73 = GPIO_MODE_NATIVE, /* Native */
383 .gpio74 = GPIO_MODE_NATIVE, /* Native */
384 .gpio75 = GPIO_MODE_NATIVE, /* Native */
385};
386
387static const struct pch_gpio_set3 pch_gpio_set3_direction = {
388 .gpio64 = GPIO_DIR_INPUT, /* Native */
389 .gpio65 = GPIO_DIR_INPUT, /* Native */
390 .gpio66 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
391 .gpio67 = GPIO_DIR_INPUT, /* Unknown Input */
392 .gpio68 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
393 .gpio69 = GPIO_DIR_INPUT, /* Unknown Input */
394 .gpio70 = GPIO_DIR_INPUT, /* Native */
395 .gpio71 = GPIO_DIR_INPUT, /* Native */
396 .gpio72 = GPIO_DIR_INPUT, /* Native */
397 .gpio73 = GPIO_DIR_INPUT, /* Native */
398 .gpio74 = GPIO_DIR_INPUT, /* Native */
399 .gpio75 = GPIO_DIR_INPUT, /* Native */
400};
401
402static const struct pch_gpio_set3 pch_gpio_set3_level = {
403 .gpio64 = GPIO_LEVEL_LOW, /* Native */
404 .gpio65 = GPIO_LEVEL_LOW, /* Native */
405 .gpio66 = GPIO_LEVEL_LOW, /* Unknown Output LOW */
406 .gpio67 = GPIO_LEVEL_LOW, /* Unknown Input */
407 .gpio68 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
408 .gpio69 = GPIO_LEVEL_LOW, /* Unknown Input */
409 .gpio70 = GPIO_LEVEL_LOW, /* Native */
410 .gpio71 = GPIO_LEVEL_LOW, /* Native */
411 .gpio72 = GPIO_LEVEL_LOW, /* Native */
412 .gpio73 = GPIO_LEVEL_LOW, /* Native */
413 .gpio74 = GPIO_LEVEL_LOW, /* Native */
414 .gpio75 = GPIO_LEVEL_LOW, /* Native */
415};
416
417static const struct pch_gpio_set3 pch_gpio_set3_reset = {
418 .gpio64 = GPIO_RESET_PWROK,
419 .gpio65 = GPIO_RESET_PWROK,
420 .gpio66 = GPIO_RESET_PWROK,
421 .gpio67 = GPIO_RESET_PWROK,
422 .gpio68 = GPIO_RESET_PWROK,
423 .gpio69 = GPIO_RESET_PWROK,
424 .gpio70 = GPIO_RESET_PWROK,
425 .gpio71 = GPIO_RESET_PWROK,
426 .gpio72 = GPIO_RESET_PWROK,
427 .gpio73 = GPIO_RESET_PWROK,
428 .gpio74 = GPIO_RESET_PWROK,
429 .gpio75 = GPIO_RESET_PWROK,
430};
431
432const struct pch_gpio_map mainboard_gpio_map = {
433 .set1 = {
434 .mode = &pch_gpio_set1_mode,
435 .direction = &pch_gpio_set1_direction,
436 .level = &pch_gpio_set1_level,
437 .reset = &pch_gpio_set1_reset,
438 .invert = &pch_gpio_set1_invert,
439 .blink = &pch_gpio_set1_blink,
440 },
441 .set2 = {
442 .mode = &pch_gpio_set2_mode,
443 .direction = &pch_gpio_set2_direction,
444 .level = &pch_gpio_set2_level,
445 .reset = &pch_gpio_set2_reset,
446 },
447 .set3 = {
448 .mode = &pch_gpio_set3_mode,
449 .direction = &pch_gpio_set3_direction,
450 .level = &pch_gpio_set3_level,
451 .reset = &pch_gpio_set3_reset,
452 },
453};