blob: 18fb1ca876d0f9d0743d883e426857c84011af57 [file] [log] [blame]
Dennis Wassenbergbd105162015-09-10 12:20:58 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2016 secunet Security Networks AG
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16DefinitionBlock(
17 "dsdt.aml",
18 "DSDT",
19 0x03, // DSDT revision: ACPI v3.0
20 "COREv4", // OEM id
21 "COREBOOT", // OEM table id
22 0x20141018 // OEM revision
23)
24{
25 #include <southbridge/intel/bd82x6x/acpi/platform.asl>
26
27 // Some generic macros
28 #include "acpi/platform.asl"
29 #include "acpi/mainboard.asl"
30
31 // global NVS and variables
32 #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
33
34 #include "acpi/thermal.asl"
35
36 #include "acpi/alsd.asl"
37
38 #include <cpu/intel/model_206ax/acpi/cpu.asl>
39
40 Scope (\_SB) {
41 Device (PCI0)
42 {
43 #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
44 #include <southbridge/intel/bd82x6x/acpi/pch.asl>
45 #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
46
47 #include <acpi/brightness_levels.asl>
48 }
49 }
50
51 /* Chipset specific sleep states */
52 #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
53}