Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 16 | #include <stdint.h> |
| 17 | #include <string.h> |
| 18 | #include <device/pci_def.h> |
| 19 | #include <arch/io.h> |
| 20 | #include <device/pnp_def.h> |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 21 | #include <cpu/x86/lapic.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 22 | #include <pc80/mc146818rtc.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 23 | #include <console/console.h> |
Patrick Georgi | 9bd9a90 | 2010-11-20 10:31:00 +0000 | [diff] [blame] | 24 | #include <spd.h> |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 25 | #include <cpu/amd/model_fxx_rev.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 26 | #include <northbridge/amd/amdk8/raminit.h> |
Edward O'Callaghan | ebe3a7a | 2015-01-05 00:27:54 +1100 | [diff] [blame] | 27 | #include <delay.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 28 | #include <cpu/x86/lapic.h> |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 29 | #include "northbridge/amd/amdk8/reset_test.c" |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 30 | #include <superio/ite/common/ite.h> |
| 31 | #include <superio/ite/it8718f/it8718f.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 32 | #include <cpu/x86/bist.h> |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 33 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 34 | #include <southbridge/amd/sb700/sb700.h> |
| 35 | #include <southbridge/amd/sb700/smbus.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 36 | #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 37 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 38 | unsigned get_sbdn(unsigned bus); |
| 39 | |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 40 | #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) |
| 41 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 42 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
| 43 | static void activate_spd_rom(const struct mem_controller *ctrl) { } |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 44 | |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 45 | static inline int spd_read_byte(u32 device, u32 address) |
| 46 | { |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 47 | return do_smbus_read_byte(SMBUS_IO_BASE, device, address); |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 48 | } |
| 49 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 50 | #include "southbridge/amd/rs780/early_setup.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 51 | #include <northbridge/amd/amdk8/amdk8.h> |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 52 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 53 | #include "northbridge/amd/amdk8/raminit_f.c" |
| 54 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 55 | #include "lib/generic_sdram.c" |
| 56 | #include "resourcemap.c" |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 57 | #include "cpu/amd/dualcore/dualcore.c" |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 58 | #include "cpu/amd/model_fxx/init_cpus.c" |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 59 | #include "cpu/amd/model_fxx/fidvid.c" |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 60 | #include "northbridge/amd/amdk8/early_ht.c" |
| 61 | |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 62 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 63 | { |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 64 | static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; |
| 65 | int needs_reset = 0; |
| 66 | u32 bsp_apicid = 0; |
| 67 | msr_t msr; |
| 68 | struct cpuid_result cpuid1; |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 69 | struct sys_info *sysinfo = &sysinfo_car; |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 70 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 71 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | 776b85b | 2010-03-18 16:18:58 +0000 | [diff] [blame] | 72 | /* Nothing special needs to be done to find bus 0 */ |
| 73 | /* Allow the HT devices to be found */ |
| 74 | enumerate_ht_chain(); |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 75 | /* sb7xx_51xx_lpc_port80(); */ |
| 76 | sb7xx_51xx_pci_port80(); |
Patrick Georgi | 776b85b | 2010-03-18 16:18:58 +0000 | [diff] [blame] | 77 | } |
| 78 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 79 | if (bist == 0) |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 80 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 81 | |
| 82 | enable_rs780_dev8(); |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 83 | sb7xx_51xx_lpc_init(); |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 84 | |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 85 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Uwe Hermann | b015d02 | 2010-09-24 18:18:20 +0000 | [diff] [blame] | 86 | |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 87 | console_init(); |
| 88 | |
| 89 | /* Halt if there was a built in self test failure */ |
| 90 | report_bist_failure(bist); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 91 | printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 92 | |
| 93 | setup_mahogany_resource_map(); |
| 94 | |
| 95 | setup_coherent_ht_domain(); |
| 96 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 97 | #if CONFIG_LOGICAL_CPUS |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 98 | /* It is said that we should start core1 after all core0 launched */ |
| 99 | wait_all_core0_started(); |
| 100 | start_other_cores(); |
| 101 | #endif |
| 102 | wait_all_aps_started(bsp_apicid); |
| 103 | |
| 104 | ht_setup_chains_x(sysinfo); |
| 105 | |
| 106 | /* run _early_setup before soft-reset. */ |
| 107 | rs780_early_setup(); |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 108 | sb7xx_51xx_early_setup(); |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 109 | |
| 110 | /* Check to see if processor is capable of changing FIDVID */ |
| 111 | /* otherwise it will throw a GP# when reading FIDVID_STATUS */ |
| 112 | cpuid1 = cpuid(0x80000007); |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 113 | if ((cpuid1.edx & 0x6) == 0x6) { |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 114 | /* Read FIDVID_STATUS */ |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame] | 115 | msr = rdmsr(0xc0010042); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 116 | printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 117 | |
| 118 | enable_fid_change(); |
| 119 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 120 | init_fidvid_bsp(bsp_apicid); |
| 121 | |
| 122 | /* show final fid and vid */ |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame] | 123 | msr = rdmsr(0xc0010042); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 124 | printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 125 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 126 | printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | needs_reset = optimize_link_coherent_ht(); |
| 130 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 131 | rs780_htinit(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 132 | printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 133 | |
| 134 | if (needs_reset) { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 135 | printk(BIOS_INFO, "ht reset -\n"); |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 136 | soft_reset(); |
| 137 | } |
| 138 | |
| 139 | allow_all_aps_stop(bsp_apicid); |
| 140 | |
| 141 | /* It's the time to set ctrl now; */ |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 142 | printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n", |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 143 | sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 144 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 145 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 146 | |
| 147 | rs780_before_pci_init(); |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 148 | sb7xx_51xx_before_pci_init(); |
Zheng Bao | dec279f | 2010-03-16 01:42:50 +0000 | [diff] [blame] | 149 | |
| 150 | post_cache_as_ram(); |
| 151 | } |