Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 1 | config SOC_INTEL_ICELAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Icelake support |
| 5 | |
| 6 | if SOC_INTEL_ICELAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
| 11 | select ARCH_BOOTBLOCK_X86_32 |
| 12 | select ARCH_RAMSTAGE_X86_32 |
| 13 | select ARCH_ROMSTAGE_X86_32 |
| 14 | select ARCH_VERSTAGE_X86_32 |
| 15 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 16 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 17 | select C_ENVIRONMENT_BOOTBLOCK |
| 18 | select CACHE_MRC_SETTINGS |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 19 | select COMMON_FADT |
| 20 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Subrata Banik | ffb83be | 2019-04-29 13:58:43 +0530 | [diff] [blame] | 21 | select FSP_M_XIP |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 22 | select GENERIC_GPIO_LIB |
| 23 | select HAVE_FSP_GOP |
| 24 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 25 | select HAVE_SMI_HANDLER |
| 26 | select IDT_IN_EVERY_STAGE |
| 27 | select INTEL_GMA_ACPI |
| 28 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 29 | select IOAPIC |
| 30 | select MRC_SETTINGS_PROTECT |
| 31 | select PARALLEL_MP |
| 32 | select PARALLEL_MP_AP_WORK |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 33 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | 55fb6b4 | 2018-12-19 16:50:57 +0530 | [diff] [blame] | 34 | select PLATFORM_USES_FSP2_1 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 35 | select REG_SCRIPT |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 36 | select SMP |
| 37 | select SOC_AHCI_PORT_IMPLEMENTED_INVERT |
| 38 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
| 39 | select SOC_INTEL_COMMON |
| 40 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 41 | select SOC_INTEL_COMMON_BLOCK |
| 42 | select SOC_INTEL_COMMON_BLOCK_ACPI |
| 43 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
| 44 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 45 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 46 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 47 | select SOC_INTEL_COMMON_BLOCK_HDA |
| 48 | select SOC_INTEL_COMMON_BLOCK_SA |
| 49 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 50 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
| 51 | select SOC_INTEL_COMMON_PCH_BASE |
| 52 | select SOC_INTEL_COMMON_RESET |
| 53 | select SSE2 |
| 54 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 55 | select TSC_CONSTANT_RATE |
| 56 | select TSC_MONOTONIC_TIMER |
| 57 | select UDELAY_TSC |
| 58 | select UDK_2017_BINDING |
| 59 | select DISPLAY_FSP_VERSION_INFO |
Subrata Banik | a0368a0 | 2019-06-04 14:16:02 +0530 | [diff] [blame] | 60 | select HECI_DISABLE_USING_SMM |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 61 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 62 | config DCACHE_RAM_BASE |
| 63 | default 0xfef00000 |
| 64 | |
| 65 | config DCACHE_RAM_SIZE |
| 66 | default 0x40000 |
| 67 | help |
| 68 | The size of the cache-as-ram region required during bootblock |
| 69 | and/or romstage. |
| 70 | |
| 71 | config DCACHE_BSP_STACK_SIZE |
| 72 | hex |
Aamir Bohra | 23012a0 | 2018-10-09 20:33:16 +0530 | [diff] [blame] | 73 | default 0x20000 if FSP_USES_CB_STACK |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 74 | default 0x4000 |
| 75 | help |
| 76 | The amount of anticipated stack usage in CAR by bootblock and |
| 77 | other stages. |
| 78 | |
Subrata Banik | 1d260e6 | 2019-09-09 13:55:42 +0530 | [diff] [blame] | 79 | config FSP_TEMP_RAM_SIZE |
| 80 | hex |
| 81 | depends on FSP_USES_CB_STACK |
| 82 | default 0x10000 |
| 83 | help |
| 84 | The amount of anticipated heap usage in CAR by FSP. |
| 85 | Refer to Platform FSP integration guide document to know |
| 86 | the exact FSP requirement for Heap setup. |
| 87 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 88 | config IFD_CHIPSET |
| 89 | string |
| 90 | default "icl" |
| 91 | |
| 92 | config IED_REGION_SIZE |
| 93 | hex |
| 94 | default 0x400000 |
| 95 | |
| 96 | config HEAP_SIZE |
| 97 | hex |
| 98 | default 0x8000 |
| 99 | |
| 100 | config MAX_ROOT_PORTS |
| 101 | int |
| 102 | default 16 |
| 103 | |
| 104 | config SMM_TSEG_SIZE |
| 105 | hex |
| 106 | default 0x800000 |
| 107 | |
| 108 | config SMM_RESERVED_SIZE |
| 109 | hex |
| 110 | default 0x200000 |
| 111 | |
| 112 | config PCR_BASE_ADDRESS |
| 113 | hex |
| 114 | default 0xfd000000 |
| 115 | help |
| 116 | This option allows you to select MMIO Base Address of sideband bus. |
| 117 | |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 118 | config MMCONF_BASE_ADDRESS |
| 119 | hex |
| 120 | default 0xc0000000 |
| 121 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 122 | config CPU_BCLK_MHZ |
| 123 | int |
| 124 | default 100 |
| 125 | |
| 126 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 127 | int |
| 128 | default 120 |
| 129 | |
| 130 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 131 | int |
| 132 | default 133 |
| 133 | |
| 134 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 135 | int |
| 136 | default 3 |
| 137 | |
| 138 | config SOC_INTEL_I2C_DEV_MAX |
| 139 | int |
| 140 | default 6 |
| 141 | |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 142 | config SOC_INTEL_UART_DEV_MAX |
| 143 | int |
| 144 | default 3 |
| 145 | |
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 146 | config CONSOLE_UART_BASE_ADDRESS |
| 147 | hex |
| 148 | default 0xfe032000 |
| 149 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 150 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 151 | # Clock divider parameters for 115200 baud rate |
| 152 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 153 | hex |
| 154 | default 0x30 |
| 155 | |
| 156 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 157 | hex |
| 158 | default 0xc35 |
| 159 | |
| 160 | config CHROMEOS |
| 161 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 162 | |
| 163 | config VBOOT |
| 164 | select VBOOT_SEPARATE_VERSTAGE |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 165 | select VBOOT_MUST_REQUEST_DISPLAY |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 166 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
| 167 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 168 | select VBOOT_VBNV_CMOS |
| 169 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 170 | |
| 171 | config C_ENV_BOOTBLOCK_SIZE |
| 172 | hex |
Subrata Banik | 458297c | 2019-01-07 14:24:27 +0530 | [diff] [blame] | 173 | default 0xC000 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 174 | |
| 175 | config CBFS_SIZE |
| 176 | hex |
| 177 | default 0x200000 |
| 178 | |
| 179 | choice |
| 180 | prompt "Cache-as-ram implementation" |
Angel Pons | 7ed704d | 2019-07-12 15:46:43 +0200 | [diff] [blame] | 181 | default USE_ICELAKE_CAR_NEM_ENHANCED |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 182 | help |
| 183 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 184 | |
| 185 | config USE_ICELAKE_CAR_NEM_ENHANCED |
| 186 | bool "Enhanced Non-evict mode" |
| 187 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 188 | select INTEL_CAR_NEM_ENHANCED |
| 189 | help |
| 190 | A current limitation of NEM (Non-Evict mode) is that code and data |
| 191 | sizes are derived from the requirement to not write out any modified |
| 192 | cache line. With NEM, if there is no physical memory behind the |
| 193 | cached area, the modified data will be lost and NEM results will be |
| 194 | inconsistent. ENHANCED NEM guarantees that modified data is always |
| 195 | kept in cache while clean data is replaced. |
| 196 | |
| 197 | config USE_ICELAKE_FSP_CAR |
| 198 | bool "Use FSP CAR" |
| 199 | select FSP_CAR |
| 200 | help |
| 201 | Use FSP APIs to initialize and tear down the Cache-As-Ram. |
| 202 | |
| 203 | endchoice |
| 204 | |
| 205 | config FSP_HEADER_PATH |
Patrick Georgi | c6382cd | 2018-10-26 22:03:17 +0200 | [diff] [blame] | 206 | string "Location of FSP headers" |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 207 | default "src/vendorcode/intel/fsp/fsp2_0/icelake/" |
| 208 | |
| 209 | config FSP_FD_PATH |
| 210 | string |
| 211 | depends on FSP_USE_REPO |
| 212 | default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" |
| 213 | |
Subrata Banik | b14b55d | 2019-07-12 18:28:56 +0530 | [diff] [blame] | 214 | config ENABLE_DISPLAY_OVER_EXT_PCIE_GFX |
| 215 | bool "Enable display over external PCIE GFX card" |
| 216 | select ALWAYS_LOAD_OPROM |
| 217 | help |
| 218 | It's possible to bring display through external graphics card over PCIE |
| 219 | in coreboot. This option enables graphics initialization with external |
| 220 | graphics card. |
| 221 | |
| 222 | Selected by mainboard that runs OpRom to perform display |
| 223 | initialization over attached PCIe GFX card. |
| 224 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 225 | endif |