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Eric Biedermanfcd5ace2004-10-14 19:29:29 +00001/*
Stefan Reinauercdc5cc62007-04-24 18:40:02 +00002 * mtrr.c: setting MTRR to decent values for cache initialization on P6
Eric Biedermanfcd5ace2004-10-14 19:29:29 +00003 *
4 * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel
5 *
6 * Copyright 2000 Silicon Integrated System Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
24 */
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000025
Yinghai Lu953e0f62005-01-06 04:55:19 +000026/*
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000027 2005.1 yhlu add NC support to spare mtrrs for 64G memory above installed
28 2005.6 Eric add address bit in x86_setup_mtrrs
29 2005.6 yhlu split x86_setup_var_mtrrs and x86_setup_fixed_mtrrs,
30 for AMD, it will not use x86_setup_fixed_mtrrs
Yinghai Lu953e0f62005-01-06 04:55:19 +000031*/
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000032
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +000033#include <stddef.h>
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000034#include <console/console.h>
35#include <device/device.h>
36#include <cpu/x86/msr.h>
37#include <cpu/x86/mtrr.h>
38#include <cpu/x86/cache.h>
Sven Schnelleadfbcb792012-01-10 12:01:43 +010039#include <arch/cpu.h>
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000040
Myles Watsonec0ee642009-10-19 16:21:30 +000041#if CONFIG_GFXUMA
Stefan Reinauer7f86ed12009-02-12 16:02:16 +000042extern uint64_t uma_memory_base, uma_memory_size;
43#endif
44
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000045static unsigned int mtrr_msr[] = {
46 MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
47 MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
48 MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
49};
50
51
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000052void enable_fixed_mtrr(void)
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000053{
54 msr_t msr;
55
56 msr = rdmsr(MTRRdefType_MSR);
57 msr.lo |= 0xc00;
58 wrmsr(MTRRdefType_MSR, msr);
59}
60
61static void enable_var_mtrr(void)
62{
63 msr_t msr;
64
65 msr = rdmsr(MTRRdefType_MSR);
Kevin O'Connor5bb9fd62011-01-19 06:32:35 +000066 msr.lo |= MTRRdefTypeEn;
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000067 wrmsr(MTRRdefType_MSR, msr);
68}
69
70/* setting variable mtrr, comes from linux kernel source */
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000071static void set_var_mtrr(
Stefan Reinauer14e22772010-04-27 06:56:47 +000072 unsigned int reg, unsigned long basek, unsigned long sizek,
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000073 unsigned char type, unsigned address_bits)
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000074{
75 msr_t base, mask;
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000076 unsigned address_mask_high;
77
Yinghai Lud4b278c2006-10-04 20:46:15 +000078 if (reg >= 8)
79 return;
80
81 // it is recommended that we disable and enable cache when we
82 // do this.
83 if (sizek == 0) {
84 disable_cache();
Stefan Reinauer14e22772010-04-27 06:56:47 +000085
Yinghai Lud4b278c2006-10-04 20:46:15 +000086 msr_t zero;
87 zero.lo = zero.hi = 0;
88 /* The invalid bit is kept in the mask, so we simply clear the
89 relevant mask register to disable a range. */
90 wrmsr (MTRRphysMask_MSR(reg), zero);
91
92 enable_cache();
93 return;
94 }
95
96
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000097 address_mask_high = ((1u << (address_bits - 32u)) - 1u);
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000098
99 base.hi = basek >> 22;
100 base.lo = basek << 10;
101
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000102 printk(BIOS_SPEW, "ADDRESS_MASK_HIGH=%#x\n", address_mask_high);
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000103
104 if (sizek < 4*1024*1024) {
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000105 mask.hi = address_mask_high;
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000106 mask.lo = ~((sizek << 10) -1);
107 }
108 else {
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000109 mask.hi = address_mask_high & (~((sizek >> 22) -1));
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000110 mask.lo = 0;
111 }
112
Stefan Reinauer14e22772010-04-27 06:56:47 +0000113 // it is recommended that we disable and enable cache when we
114 // do this.
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000115 disable_cache();
Yinghai Lud4b278c2006-10-04 20:46:15 +0000116
117 /* Bit 32-35 of MTRRphysMask should be set to 1 */
118 base.lo |= type;
Kevin O'Connor5bb9fd62011-01-19 06:32:35 +0000119 mask.lo |= MTRRphysMaskValid;
Yinghai Lud4b278c2006-10-04 20:46:15 +0000120 wrmsr (MTRRphysBase_MSR(reg), base);
121 wrmsr (MTRRphysMask_MSR(reg), mask);
122
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000123 enable_cache();
124}
125
126/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
127static inline unsigned int fms(unsigned int x)
128{
129 int r;
130
131 __asm__("bsrl %1,%0\n\t"
132 "jnz 1f\n\t"
133 "movl $0,%0\n"
134 "1:" : "=r" (r) : "g" (x));
135 return r;
136}
137
Marc Jones5cbdc1e2009-04-01 22:07:53 +0000138/* fls: find least sigificant bit set */
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000139static inline unsigned int fls(unsigned int x)
140{
141 int r;
142
143 __asm__("bsfl %1,%0\n\t"
144 "jnz 1f\n\t"
145 "movl $32,%0\n"
146 "1:" : "=r" (r) : "g" (x));
147 return r;
148}
149
150/* setting up variable and fixed mtrr
151 *
152 * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement:
153 * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
154 * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous
155 * requirement. So a 8K range must be 8K aligned not 4K aligned.
156 *
157 * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]).
158 * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]).
159 * A 124MB (128MB - 4MB SMA) example:
160 * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB).
161 * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions.
162 *
163 * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible,
164 * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula
165 * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used.
166 * The same 124MB example:
167 * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB)
168 * or a 156MB (128MB + 32MB - 4MB SMA) example:
169 * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
170 */
171/* 2 MTRRS are reserved for the operating system */
Stefan Reinauer7f86ed12009-02-12 16:02:16 +0000172#if 1
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000173#define BIOS_MTRRS 6
174#define OS_MTRRS 2
175#else
176#define BIOS_MTRRS 8
177#define OS_MTRRS 0
178#endif
179#define MTRRS (BIOS_MTRRS + OS_MTRRS)
180
181
182static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
183{
184 unsigned int i;
185 unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
186 msr_t msr;
187 msr.lo = msr.hi = 0; /* Shut up gcc */
188 for(i = first; i < last; i++) {
189 /* When I switch to a new msr read it in */
190 if (fixed_msr != i >> 3) {
191 /* But first write out the old msr */
192 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
193 disable_cache();
194 wrmsr(mtrr_msr[fixed_msr], msr);
195 enable_cache();
196 }
197 fixed_msr = i>>3;
198 msr = rdmsr(mtrr_msr[fixed_msr]);
199 }
200 if ((i & 7) < 4) {
201 msr.lo &= ~(0xff << ((i&3)*8));
202 msr.lo |= type << ((i&3)*8);
203 } else {
204 msr.hi &= ~(0xff << ((i&3)*8));
205 msr.hi |= type << ((i&3)*8);
206 }
207 }
208 /* Write out the final msr */
209 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
210 disable_cache();
211 wrmsr(mtrr_msr[fixed_msr], msr);
212 enable_cache();
213 }
214}
215
216static unsigned fixed_mtrr_index(unsigned long addrk)
217{
218 unsigned index;
219 index = (addrk - 0) >> 6;
220 if (index >= 8) {
221 index = ((addrk - 8*64) >> 4) + 8;
222 }
223 if (index >= 24) {
224 index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
225 }
226 if (index > NUM_FIXED_RANGES) {
227 index = NUM_FIXED_RANGES;
228 }
229 return index;
230}
231
Stefan Reinauer14e22772010-04-27 06:56:47 +0000232static unsigned int range_to_mtrr(unsigned int reg,
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000233 unsigned long range_startk, unsigned long range_sizek,
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000234 unsigned long next_range_startk, unsigned char type,
235 unsigned int address_bits, unsigned int above4gb)
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000236{
Carl-Daniel Hailfinger7dde1da2009-02-11 16:57:32 +0000237 if (!range_sizek) {
Stefan Reinauer7f86ed12009-02-12 16:02:16 +0000238 /* If there's no MTRR hole, this function will bail out
239 * here when called for the hole.
240 */
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000241 printk(BIOS_SPEW, "Zero-sized MTRR range @%ldKB\n", range_startk);
Carl-Daniel Hailfinger7dde1da2009-02-11 16:57:32 +0000242 return reg;
243 }
Stefan Reinauer7f86ed12009-02-12 16:02:16 +0000244
Carl-Daniel Hailfinger7dde1da2009-02-11 16:57:32 +0000245 if (reg >= BIOS_MTRRS) {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000246 printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n",
Stefan Reinauer7f86ed12009-02-12 16:02:16 +0000247 range_startk >>10, range_sizek >> 10,
248 (type==MTRR_TYPE_UNCACHEABLE)?"UC":
249 ((type==MTRR_TYPE_WRBACK)?"WB":"Other") );
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000250 return reg;
251 }
Stefan Reinauer7f86ed12009-02-12 16:02:16 +0000252
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000253 while(range_sizek) {
254 unsigned long max_align, align;
255 unsigned long sizek;
256 /* Compute the maximum size I can make a range */
257 max_align = fls(range_startk);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000258 align = fms(range_sizek);
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000259 if (align > max_align) {
260 align = max_align;
261 }
262 sizek = 1 << align;
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000263 printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000264 reg, range_startk >>10, sizek >> 10,
265 (type==MTRR_TYPE_UNCACHEABLE)?"UC":
266 ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
Yinghai Lu63601872005-01-27 22:48:12 +0000267 );
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000268
269 /* if range is above 4GB, MTRR is needed
270 * only if above4gb flag is set
271 */
272 if (range_startk < 0x100000000ull / 1024 || above4gb)
273 set_var_mtrr(reg++, range_startk, sizek, type, address_bits);
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000274 range_startk += sizek;
275 range_sizek -= sizek;
Carl-Daniel Hailfinger7dde1da2009-02-11 16:57:32 +0000276 if (reg >= BIOS_MTRRS) {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000277 printk(BIOS_ERR, "Running out of variable MTRRs!\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000278 break;
Carl-Daniel Hailfinger7dde1da2009-02-11 16:57:32 +0000279 }
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000280 }
281 return reg;
282}
283
Stefan Reinauer14e22772010-04-27 06:56:47 +0000284static unsigned long resk(uint64_t value)
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000285{
286 unsigned long resultk;
287 if (value < (1ULL << 42)) {
288 resultk = value >> 10;
289 }
290 else {
291 resultk = 0xffffffff;
292 }
293 return resultk;
294}
295
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000296static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res)
297{
298 unsigned int start_mtrr;
299 unsigned int last_mtrr;
300 start_mtrr = fixed_mtrr_index(resk(res->base));
301 last_mtrr = fixed_mtrr_index(resk((res->base + res->size)));
302 if (start_mtrr >= NUM_FIXED_RANGES) {
303 return;
304 }
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000305 printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n",
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000306 start_mtrr, last_mtrr);
307 set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000308
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000309}
310
Yinghai Lu21332b82007-04-06 19:49:05 +0000311#ifndef CONFIG_VAR_MTRR_HOLE
312#define CONFIG_VAR_MTRR_HOLE 1
313#endif
314
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000315struct var_mtrr_state {
316 unsigned long range_startk, range_sizek;
317 unsigned int reg;
Yinghai Lu63601872005-01-27 22:48:12 +0000318 unsigned long hole_startk, hole_sizek;
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000319 unsigned int address_bits;
320 unsigned int above4gb; /* Set if MTRRs are needed for DRAM above 4GB */
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000321};
322
323void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
324{
325 struct var_mtrr_state *state = gp;
326 unsigned long basek, sizek;
327 if (state->reg >= BIOS_MTRRS)
328 return;
329 basek = resk(res->base);
330 sizek = resk(res->size);
331 /* See if I can merge with the last range
332 * Either I am below 1M and the fixed mtrrs handle it, or
333 * the ranges touch.
334 */
335 if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) {
336 unsigned long endk = basek + sizek;
337 state->range_sizek = endk - state->range_startk;
338 return;
339 }
340 /* Write the range mtrrs */
341 if (state->range_sizek != 0) {
Yinghai Lu21332b82007-04-06 19:49:05 +0000342#if CONFIG_VAR_MTRR_HOLE
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000343 if (state->hole_sizek == 0) {
344 /* We need to put that on to hole */
345 unsigned long endk = basek + sizek;
Yinghai Lu63601872005-01-27 22:48:12 +0000346 state->hole_startk = state->range_startk + state->range_sizek;
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000347 state->hole_sizek = basek - state->hole_startk;
348 state->range_sizek = endk - state->range_startk;
Yinghai Lu63601872005-01-27 22:48:12 +0000349 return;
350 }
Yinghai Lu21332b82007-04-06 19:49:05 +0000351#endif
Stefan Reinauer14e22772010-04-27 06:56:47 +0000352 state->reg = range_to_mtrr(state->reg, state->range_startk,
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000353 state->range_sizek, basek, MTRR_TYPE_WRBACK,
354 state->address_bits, state->above4gb);
Yinghai Lu21332b82007-04-06 19:49:05 +0000355#if CONFIG_VAR_MTRR_HOLE
Stefan Reinauer14e22772010-04-27 06:56:47 +0000356 state->reg = range_to_mtrr(state->reg, state->hole_startk,
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000357 state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE,
358 state->address_bits, state->above4gb);
Yinghai Lu21332b82007-04-06 19:49:05 +0000359#endif
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000360 state->range_startk = 0;
361 state->range_sizek = 0;
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000362 state->hole_startk = 0;
363 state->hole_sizek = 0;
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000364 }
Stefan Reinauer14e22772010-04-27 06:56:47 +0000365 /* Allocate an msr */
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000366 printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek);
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000367 state->range_startk = basek;
368 state->range_sizek = sizek;
369}
370
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000371void x86_setup_fixed_mtrrs(void)
372{
373 /* Try this the simple way of incrementally adding together
Stefan Reinauer14e22772010-04-27 06:56:47 +0000374 * mtrrs. If this doesn't work out we can get smart again
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000375 * and clear out the mtrrs.
376 */
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000377
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000378 printk(BIOS_DEBUG, "\n");
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000379 /* Initialized the fixed_mtrrs to uncached */
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000380 printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: UC\n",
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000381 0, NUM_FIXED_RANGES);
382 set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
383
384 /* Now see which of the fixed mtrrs cover ram.
385 */
386 search_global_resources(
387 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
388 set_fixed_mtrr_resource, NULL);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000389 printk(BIOS_DEBUG, "DONE fixed MTRRs\n");
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000390
391 /* enable fixed MTRR */
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000392 printk(BIOS_SPEW, "call enable_fixed_mtrr()\n");
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000393 enable_fixed_mtrr();
394
395}
Stefan Reinauer7f86ed12009-02-12 16:02:16 +0000396
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000397void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000398/* this routine needs to know how many address bits a given processor
Stefan Reinauer14e22772010-04-27 06:56:47 +0000399 * supports. CPUs get grumpy when you set too many bits in
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000400 * their mtrr registers :( I would generically call cpuid here
401 * and find out how many physically supported but some cpus are
402 * buggy, and report more bits then they actually support.
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000403 * If above4gb flag is set, variable MTRR ranges must be used to
404 * set cacheability of DRAM above 4GB. If above4gb flag is clear,
405 * some other mechanism is controlling cacheability of DRAM above 4GB.
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000406 */
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000407{
408 /* Try this the simple way of incrementally adding together
Stefan Reinauer14e22772010-04-27 06:56:47 +0000409 * mtrrs. If this doesn't work out we can get smart again
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000410 * and clear out the mtrrs.
411 */
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000412 struct var_mtrr_state var_state;
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000413
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000414 /* Cache as many memory areas as possible */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000415 /* FIXME is there an algorithm for computing the optimal set of mtrrs?
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000416 * In some cases it is definitely possible to do better.
417 */
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000418 var_state.range_startk = 0;
419 var_state.range_sizek = 0;
Yinghai Lu63601872005-01-27 22:48:12 +0000420 var_state.hole_startk = 0;
421 var_state.hole_sizek = 0;
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000422 var_state.reg = 0;
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000423 var_state.address_bits = address_bits;
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000424 var_state.above4gb = above4gb;
Stefan Reinauer7f86ed12009-02-12 16:02:16 +0000425
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000426 search_global_resources(
427 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
428 set_var_mtrr_resource, &var_state);
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000429
Zheng Baoedee9eb2009-08-11 03:18:11 +0000430#if (CONFIG_GFXUMA == 1) /* UMA or SP. */
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000431 /* For now we assume the UMA space is at the end of memory below 4GB */
Stefan Reinauer7f86ed12009-02-12 16:02:16 +0000432 if (var_state.hole_startk || var_state.hole_sizek) {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000433 printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n");
Stefan Reinauer7f86ed12009-02-12 16:02:16 +0000434 } else {
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000435#if CONFIG_VAR_MTRR_HOLE
Stefan Reinauer7f86ed12009-02-12 16:02:16 +0000436 // Increase the base range and set up UMA as an UC hole instead
437 var_state.range_sizek += (uma_memory_size >> 10);
Yinghai Lu953e0f62005-01-06 04:55:19 +0000438
Stefan Reinauer7f86ed12009-02-12 16:02:16 +0000439 var_state.hole_startk = (uma_memory_base >> 10);
440 var_state.hole_sizek = (uma_memory_size >> 10);
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000441#endif
Stefan Reinauer7f86ed12009-02-12 16:02:16 +0000442 }
443#endif
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000444 /* Write the last range */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000445 var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk,
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000446 var_state.range_sizek, 0, MTRR_TYPE_WRBACK,
447 var_state.address_bits, var_state.above4gb);
Yinghai Lu21332b82007-04-06 19:49:05 +0000448#if CONFIG_VAR_MTRR_HOLE
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000449 var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000450 var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE,
451 var_state.address_bits, var_state.above4gb);
Yinghai Lu21332b82007-04-06 19:49:05 +0000452#endif
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000453 printk(BIOS_DEBUG, "DONE variable MTRRs\n");
454 printk(BIOS_DEBUG, "Clear out the extra MTRR's\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000455 /* Clear out the extra MTRR's */
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000456 while(var_state.reg < MTRRS) {
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000457 set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000458 }
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000459 printk(BIOS_SPEW, "call enable_var_mtrr()\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000460 enable_var_mtrr();
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000461 printk(BIOS_SPEW, "Leave %s\n", __func__);
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000462 post_code(0x6A);
463}
464
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000465
Sven Schnelleadfbcb792012-01-10 12:01:43 +0100466void x86_setup_mtrrs(void)
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000467{
Sven Schnelleadfbcb792012-01-10 12:01:43 +0100468 int address_size;
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000469 x86_setup_fixed_mtrrs();
Sven Schnelleadfbcb792012-01-10 12:01:43 +0100470 address_size = cpu_phys_address_size();
471 printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size);
472 x86_setup_var_mtrrs(address_size, 1);
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000473}
474
475
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000476int x86_mtrr_check(void)
477{
478 /* Only Pentium Pro and later have MTRR */
479 msr_t msr;
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000480 printk(BIOS_DEBUG, "\nMTRR check\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000481
482 msr = rdmsr(0x2ff);
483 msr.lo >>= 10;
484
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000485 printk(BIOS_DEBUG, "Fixed MTRRs : ");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000486 if (msr.lo & 0x01)
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000487 printk(BIOS_DEBUG, "Enabled\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000488 else
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000489 printk(BIOS_DEBUG, "Disabled\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000490
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000491 printk(BIOS_DEBUG, "Variable MTRRs: ");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000492 if (msr.lo & 0x02)
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000493 printk(BIOS_DEBUG, "Enabled\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000494 else
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000495 printk(BIOS_DEBUG, "Disabled\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000496
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000497 printk(BIOS_DEBUG, "\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000498
499 post_code(0x93);
500 return ((int) msr.lo);
501}