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Jon Harrisoncfb9cd22009-07-01 10:57:25 +00001/*
Uwe Hermannc70e9fc2010-02-15 23:10:19 +00002 * This file is part of the coreboot project.
Jon Harrisoncfb9cd22009-07-01 10:57:25 +00003 *
Uwe Hermannc70e9fc2010-02-15 23:10:19 +00004 * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
5 * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk
Jon Harrisoncfb9cd22009-07-01 10:57:25 +00006 *
Uwe Hermannc70e9fc2010-02-15 23:10:19 +00007 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000011 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
Uwe Hermannc70e9fc2010-02-15 23:10:19 +000019 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000020 */
21
Stefan Reinauer14e22772010-04-27 06:56:47 +000022/*
Jon Harrison1825be22009-08-17 17:09:46 +000023 Automatically detect and set up ddr dram on the CN400 chipset.
24 Assumes DDR400 memory as no attempt is made to clock
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000025 the chipset down if slower memory is installed.
26 So far tested on:
Jon Harrison1825be22009-08-17 17:09:46 +000027 512 Mb DDR400 4 Bank / 2 Rank (1GB) (i.e. double sided)
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000028*/
Jon Harrison1825be22009-08-17 17:09:46 +000029/* ported from Via VT8263 Code*/
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000030
31#include <spd.h>
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000032#include <delay.h>
33#include <cpu/x86/mtrr.h>
34#include "cn400.h"
35
Stefan Reinauer14e22772010-04-27 06:56:47 +000036static void dimm_read(unsigned long bank,unsigned long x)
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000037{
Stefan Reinauer14e22772010-04-27 06:56:47 +000038 //unsigned long eax;
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000039 volatile unsigned long y;
40 //eax = x;
41 y = * (volatile unsigned long *) (x+ bank) ;
42
43}
44
45
46static void print_val(char *str, int val)
47{
48 print_debug(str);
49 print_debug_hex8(val);
50}
51
52/**
Stefan Reinauer14e22772010-04-27 06:56:47 +000053 * Configure the bus between the CPU and the northbridge. This might be able to
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000054 * be moved to post-ram code in the future. For the most part, these registers
55 * should not be messed around with. These are too complex to explain short of
56 * copying the datasheets into the comments, but most of these values are from
57 * the BIOS Porting Guide, so they should work on any board. If they don't,
58 * try the values from your factory BIOS.
59 *
60 * TODO: Changing the DRAM frequency doesn't work (hard lockup).
61 *
62 * @param dev The northbridge's CPU Host Interface (D0F2).
63 */
64static void c3_cpu_setup(device_t dev)
65{
66 /* Host bus interface registers (D0F2 0x50-0x67) */
67 /* Taken from CN700 and updated from running CN400 */
Jon Harrison1825be22009-08-17 17:09:46 +000068 uint8_t reg8;
Stefan Reinauer14e22772010-04-27 06:56:47 +000069
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000070 /* Host Bus I/O Circuit (see datasheet) */
71 /* Host Address Pullup/down Driving */
72 pci_write_config8(dev, 0x70, 0x33);
73 pci_write_config8(dev, 0x71, 0x44);
74 pci_write_config8(dev, 0x72, 0x33);
75 pci_write_config8(dev, 0x73, 0x44);
Stefan Reinauer14e22772010-04-27 06:56:47 +000076
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000077 /* Output Delay Stagger Control */
78 pci_write_config8(dev, 0x74, 0x70);
Stefan Reinauer14e22772010-04-27 06:56:47 +000079
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000080 /* AGTL+ I/O Circuit */
81 pci_write_config8(dev, 0x75, 0x08);
Stefan Reinauer14e22772010-04-27 06:56:47 +000082
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000083 /* AGTL+ Compensation Status */
84 pci_write_config8(dev, 0x76, 0x74);
Stefan Reinauer14e22772010-04-27 06:56:47 +000085
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000086 /* AGTL+ Auto Compensation Offest */
87 pci_write_config8(dev, 0x77, 0x00);
Jon Harrison1825be22009-08-17 17:09:46 +000088 pci_write_config8(dev, 0x78, 0x94);
Stefan Reinauer14e22772010-04-27 06:56:47 +000089
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000090 /* Request phase control */
91 pci_write_config8(dev, 0x50, 0xA8);
92
93 /* Line DRDY# Timing Control */
94 pci_write_config8(dev, 0x60, 0x00);
95 pci_write_config8(dev, 0x61, 0x00);
96 pci_write_config8(dev, 0x62, 0x00);
Stefan Reinauer14e22772010-04-27 06:56:47 +000097
Jon Harrisoncfb9cd22009-07-01 10:57:25 +000098 /* QW DRDY# Timing Control */
99 pci_write_config8(dev, 0x63, 0x00);
100 pci_write_config8(dev, 0x64, 0x00);
101 pci_write_config8(dev, 0x65, 0x00);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000102
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000103 /* Read Line Burst DRDY# Timing Control */
104 pci_write_config8(dev, 0x66, 0x00);
105 pci_write_config8(dev, 0x67, 0x00);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000106
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000107 /* CPU Interface Control */
108 pci_write_config8(dev, 0x51, 0xFE);
109 pci_write_config8(dev, 0x52, 0xEF);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000110
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000111 /* Arbitration */
112 pci_write_config8(dev, 0x53, 0x88);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000113
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000114 /* Write Policy & Reorder Latecy */
115 pci_write_config8(dev, 0x56, 0x00);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000116
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000117 /* Delivery-Trigger Control */
118 pci_write_config8(dev, 0x58, 0x00);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000119
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000120 /* IPI Control */
121 pci_write_config8(dev, 0x59, 0x30);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000122
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000123 /* CPU Misc Control */
124 pci_write_config8(dev, 0x5C, 0x00);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000125
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000126 /* Write Policy */
127 pci_write_config8(dev, 0x5d, 0xb2);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000128
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000129 /* Bandwidth Timer */
130 pci_write_config8(dev, 0x5e, 0x88);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000131
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000132 /* CPU Miscellaneous Control */
133 pci_write_config8(dev, 0x5f, 0xc7);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000134
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000135 /* CPU Miscellaneous Control */
136 pci_write_config8(dev, 0x55, 0x28);
Jon Harrison1825be22009-08-17 17:09:46 +0000137 pci_write_config8(dev, 0x57, 0x69);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000138
Jon Harrison1825be22009-08-17 17:09:46 +0000139 /* CPU Host Bus Final Setup */
140 reg8 = pci_read_config8(dev, 0x54);
141 reg8 |= 0x08;
142 pci_write_config8(dev, 0x54, reg8);
143
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000144}
Stefan Reinauer14e22772010-04-27 06:56:47 +0000145
146static void ddr_ram_setup(void)
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000147{
148 uint8_t b, c, bank, ma;
149 uint16_t i;
150 unsigned long bank_address;
Stefan Reinauer14e22772010-04-27 06:56:47 +0000151
152
153 print_debug("CN400 RAM init starting\n");
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000154
155 pci_write_config8(ctrl.d0f7, 0x75, 0x08);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000156
157
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000158 /* No Interleaving or Multi Page */
159 pci_write_config8(ctrl.d0f3, 0x69, 0x00);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000160 pci_write_config8(ctrl.d0f3, 0x6b, 0x10);
161
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000162/*
163 DRAM MA Map Type Device 0 Fn3 Offset 50-51
164
165 Determine memory addressing based on the module's memory technology and
166 arrangement. See Table 4-9 of Intel's 82443GX datasheet for details.
167
168 Bank 1/0 MA map type 50[7-5]
169 Bank 1/0 command rate 50[4]
170 Bank 3/2 MA map type 50[3-1]
171 Bank 3/2 command rate 50[0]
172
173
174 Read SPD byte 17, Number of banks on SDRAM device.
175*/
176 c = 0;
Uwe Hermannd773fd32010-11-20 20:23:08 +0000177 b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000178 //print_val("Detecting Memory\nNumber of Banks ",b);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000179
180 // Only supporting 4 bank chips just now
181 if( b == 4 ){
Uwe Hermannd773fd32010-11-20 20:23:08 +0000182 /* Read SPD byte 3, Number of row addresses. */
Jon Harrison1825be22009-08-17 17:09:46 +0000183 c = 0x01;
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000184 bank = 0x40;
Uwe Hermannd773fd32010-11-20 20:23:08 +0000185 b = smbus_read_byte(DIMM0, SPD_NUM_ROWS);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000186 //print_val("\nNumber of Rows ", b);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000187
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000188 if( b >= 0x0d ){ // 256/512Mb
Stefan Reinauer14e22772010-04-27 06:56:47 +0000189
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000190 if (b == 0x0e)
191 bank = 0x48;
192 else
193 bank = 0x44;
Stefan Reinauer14e22772010-04-27 06:56:47 +0000194
Uwe Hermannd773fd32010-11-20 20:23:08 +0000195 /* Read SPD byte 13, Primary DRAM width. */
196 b = smbus_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000197 //print_val("\nPrimary DRAM width", b);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000198 if( b != 4 ) // not 64/128Mb (x4)
Jon Harrison1825be22009-08-17 17:09:46 +0000199 c = 0x81; // 256Mb
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000200 }
201
Uwe Hermannd773fd32010-11-20 20:23:08 +0000202 /* Read SPD byte 4, Number of column addresses. */
203 b = smbus_read_byte(DIMM0, SPD_NUM_COLUMNS);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000204 //print_val("\nNo Columns ",b);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000205 if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr
206 if( b == 9 ) c |= 0x40; // 9 bit col addr
207 if( b == 8 ) c |= 0x20; // 8 bit col addr
208
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000209 //print_val("\nMA type ", c);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000210 pci_write_config8(ctrl.d0f3, 0x50, c);
211
212 }
Jon Harrison1825be22009-08-17 17:09:46 +0000213
214 /* Disable Upper Banks */
215 pci_write_config8(ctrl.d0f3, 0x51, 0x00);
216
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000217/* else
218 {
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000219 die("DRAM module size is not supported by CN400\n");
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000220 }
221*/
222
223/*
224 DRAM bank size. See 4.3.1 pg 35
225
226 5a->5d set to end address for each bank. 1 bit == 32MB
227 5a = bank 0
228 5b = bank 0 + b1
229 5c = bank 0 + b1 + b2
230 5d = bank 0 + b1 + b2 + b3
231*/
232
233 // Read SPD byte 31 Module bank density
234 //c = 0;
Uwe Hermannd773fd32010-11-20 20:23:08 +0000235 b = smbus_read_byte(DIMM0, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000236 if( b & 0x02 )
Stefan Reinauer14e22772010-04-27 06:56:47 +0000237 {
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000238 c = 0x40; // 2GB
239 bank |= 0x02;
240 }
Stefan Reinauer14e22772010-04-27 06:56:47 +0000241 else if( b & 0x01)
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000242 {
243 c = 0x20; // 1GB
244 if (bank == 0x48) bank |= 0x01;
245 else bank |= 0x03;
246 }
247 else if( b & 0x80)
248 {
249 c = 0x10; // 512MB
250 if (bank == 0x44) bank |= 0x02;
251 }
Stefan Reinauer14e22772010-04-27 06:56:47 +0000252 else if( b & 0x40)
253 {
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000254 c = 0x08; // 256MB
255 if (bank == 0x44) bank |= 0x01;
256 else bank |= 0x03;
Stefan Reinauer14e22772010-04-27 06:56:47 +0000257 }
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000258 else if( b & 0x20)
259 {
260 c = 0x04; // 128MB
261 if (bank == 0x40) bank |= 0x02;
262 }
263 else if( b & 0x10)
264 {
265 c = 0x02; // 64MB
266 bank |= 0x01;
267 }
268 else if( b & 0x08) c = 0x01; // 32MB
269 else c = 0x01; // Error, use default
270
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000271 // set bank zero size
272 pci_write_config8(ctrl.d0f3, 0x40, c);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000273
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000274 // SPD byte 5 # of physical banks
Uwe Hermannd773fd32010-11-20 20:23:08 +0000275 b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000276
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000277 //print_val("\nNo Physical Banks ",b);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000278 if( b == 2)
279 {
280 c <<=1;
281 bank |= 0x80;
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000282 }
283/* else
284 {
Stefan Reinauer14e22772010-04-27 06:56:47 +0000285 die("Only a single DIMM is supported by EPIA-N(L)\n");
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000286 }
287*/
288 // set banks 1,2,3...
289 pci_write_config8(ctrl.d0f3, 0x41,c);
290 pci_write_config8(ctrl.d0f3, 0x42,c);
291 pci_write_config8(ctrl.d0f3, 0x43,c);
292 pci_write_config8(ctrl.d0f3, 0x44,c);
293 pci_write_config8(ctrl.d0f3, 0x45,c);
294 pci_write_config8(ctrl.d0f3, 0x46,c);
295 pci_write_config8(ctrl.d0f3, 0x47,c);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000296
Jon Harrison1825be22009-08-17 17:09:46 +0000297 /* Top Rank Address Mirrored to the South Bridge */
298 /* over the VLink */
299 pci_write_config8(ctrl.d0f7, 0x57, (c << 1));
300
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000301 ma = bank;
Stefan Reinauer14e22772010-04-27 06:56:47 +0000302
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000303 /* Read SPD byte 18 CAS Latency */
Uwe Hermannd773fd32010-11-20 20:23:08 +0000304 b = smbus_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000305/* print_debug("\nCAS Supported ");
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000306 if(b & 0x04)
307 print_debug("2 ");
308 if(b & 0x08)
309 print_debug("2.5 ");
310 if(b & 0x10)
311 print_debug("3");
312
Uwe Hermannd773fd32010-11-20 20:23:08 +0000313 c = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000314 print_val("\nCycle time at CL X (nS)", c);
Uwe Hermannd773fd32010-11-20 20:23:08 +0000315 c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000316 print_val("\nCycle time at CL X-0.5 (nS)", c);
Uwe Hermannd773fd32010-11-20 20:23:08 +0000317 c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000318 print_val("\nCycle time at CL X-1 (nS)", c);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000319*/
Jon Harrison1825be22009-08-17 17:09:46 +0000320 /* Scaling of Cycle Time SPD data */
321 /* 7 4 3 0 */
322 /* ns x0.1ns */
Uwe Hermannd773fd32010-11-20 20:23:08 +0000323 bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000324
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000325 if( b & 0x10 ){ // DDR offering optional CAS 3
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000326 //print_debug("\nStarting at CAS 3");
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000327 c = 0x30;
328 /* see if we can better it */
329 if( b & 0x08 ){ // DDR mandatory CAS 2.5
Uwe Hermannd773fd32010-11-20 20:23:08 +0000330 if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000331 //print_debug("\nWe can do CAS 2.5");
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000332 c = 0x20;
333 }
334 }
335 if( b & 0x04 ){ // DDR mandatory CAS 2
Uwe Hermannd773fd32010-11-20 20:23:08 +0000336 if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000337 //print_debug("\nWe can do CAS 2");
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000338 c = 0x10;
339 }
340 }
341 }else{ // no optional CAS values just 2 & 2.5
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000342 //print_debug("\nStarting at CAS 2.5");
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000343 c = 0x20; // assume CAS 2.5
344 if( b & 0x04){ // Should always happen
Uwe Hermannd773fd32010-11-20 20:23:08 +0000345 if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000346 //print_debug("\nWe can do CAS 2");
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000347 c = 0x10;
348 }
349 }
Stefan Reinauer14e22772010-04-27 06:56:47 +0000350 }
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000351
Jon Harrison1825be22009-08-17 17:09:46 +0000352 /* Scale DRAM Cycle Time to tRP/tRCD */
353 /* 7 2 1 0 */
354 /* ns x0.25ns */
355 if ( bank <= 0x50 ) bank = 0x14;
356 else if (bank <= 0x60) bank = 0x18;
357 else bank = 0x1E;
358
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000359/*
360 DRAM Timing Device 0 Fn 3 Offset 56
361
362 RAS Pulse width 56[7,6]
363 CAS Latency 56[5,4]
364 Row pre-charge 56[1,0]
365
366 SDR DDR
367 00 1T -
368 01 2T 2T
369 10 3T 2.5T
370 11 - 3T
371
372 RAS/CAS delay 56[3,2]
373
374 Determine row pre-charge time (tRP)
375
376
377 Read SPD byte 27, min row pre-charge time.
378*/
379
Uwe Hermannd773fd32010-11-20 20:23:08 +0000380 b = smbus_read_byte(DIMM0, SPD_MIN_ROW_PRECHARGE_TIME);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000381
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000382 //print_val("\ntRP ",b);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000383 if ( b >= (5 * bank)) {
384 c |= 0x03; // set tRP = 5T
385 }
386 else if ( b >= (4 * bank)) {
387 c |= 0x02; // set tRP = 4T
388 }
389 else if ( b >= (3 * bank)) {
390 c |= 0x01; // set tRP = 3T
391 }
392
393/*
394 Determine RAS to CAS delay (tRCD)
395
396 Read SPD byte 29, min row pre-charge time.
397*/
398
Uwe Hermannd773fd32010-11-20 20:23:08 +0000399 b = smbus_read_byte(DIMM0, SPD_MIN_RAS_TO_CAS_DELAY);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000400 //print_val("\ntRCD ",b);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000401
402 if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T
403 else if ( b >= (4 * bank)) c |= 0x08; // set tRCD = 4T
404 else if ( b >= (3 * bank)) c |= 0x04; // set tRCD = 3T
405
406/*
407 Determine RAS pulse width (tRAS)
408
409
410 Read SPD byte 30, device min active to pre-charge time.
411*/
412
Jon Harrison1825be22009-08-17 17:09:46 +0000413 /* tRAS is in whole ns */
414 bank = bank >> 2;
415
Uwe Hermannd773fd32010-11-20 20:23:08 +0000416 b = smbus_read_byte(DIMM0, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000417 //print_val("\ntRAS ",b);
418 //print_val("\nBank ", bank);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000419 if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T
420 else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T
421 else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T
Stefan Reinauer14e22772010-04-27 06:56:47 +0000422
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000423 /* Write DRAM Timing All Banks I */
424 pci_write_config8(ctrl.d0f3, 0x56, c);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000425
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000426 /* TWrite DRAM Timing All Banks II */
427 pci_write_config8(ctrl.d0f3, 0x57, 0x1a);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000428
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000429 /* DRAM arbitration timer */
430 pci_write_config8(ctrl.d0f3, 0x65, 0x99);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000431
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000432/*
433 DRAM Clock Device 0 Fn 3 Offset 68
434*/
Uwe Hermannd773fd32010-11-20 20:23:08 +0000435 bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000436
437 /* Setup DRAM Cycle Time */
438 if ( bank <= 0x50 )
439 {
440 /* DRAM DDR Control Alert! Alert! See also c3_cpu_setup */
441 /* This sets to 133MHz FSB / DDR400. */
442 pci_write_config8(ctrl.d0f3, 0x68, 0x85);
443 }
444 else if (bank <= 0x60)
445 {
446 /* DRAM DDR Control Alert! Alert! This hardwires to */
447 /* 133MHz FSB / DDR333. See also c3_cpu_setup */
448 pci_write_config8(ctrl.d0f3, 0x68, 0x81);
449 }
Stefan Reinauer14e22772010-04-27 06:56:47 +0000450 else
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000451 {
452 /* DRAM DDR Control Alert! Alert! This hardwires to */
453 /* 133MHz FSB / DDR266. See also c3_cpu_setup */
454 pci_write_config8(ctrl.d0f3, 0x68, 0x80);
455 }
456
457 /* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
458 udelay(200);
459
460/*
461 Determine bank interleave
462
463 Read SPD byte 17, Number of banks on SDRAM device.
464*/
465 c = 0x0F;
Uwe Hermannd773fd32010-11-20 20:23:08 +0000466 b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000467 if( b == 4) c |= 0x80;
468 else if (b == 2) c |= 0x40;
469
470 /* 4-Way Interleave With Multi-Paging (From Running System)*/
471 pci_write_config8(ctrl.d0f3, 0x69, c);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000472
Jon Harrison1825be22009-08-17 17:09:46 +0000473 /*DRAM Controller Internal Options */
474 pci_write_config8(ctrl.d0f3, 0x54, 0x01);
475
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000476 /* DRAM Arbitration Control */
477 pci_write_config8(ctrl.d0f3, 0x66, 0x82);
478
479 /* DRAM Control */
Jon Harrison1825be22009-08-17 17:09:46 +0000480 pci_write_config8(ctrl.d0f3, 0x6e, 0x80);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000481
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000482 /* Disable refresh for now */
483 pci_write_config8(ctrl.d0f3, 0x6a, 0x00);
484
Jon Harrison1825be22009-08-17 17:09:46 +0000485 /* DDR Clock Gen Duty Cycle Control */
486 pci_write_config8(ctrl.d0f3, 0xEE, 0x01);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000487
488
489 /* DRAM Clock Control */
490 pci_write_config8(ctrl.d0f3, 0x6c, 0x00);
491
492 /* DRAM Bus Turn-Around Setting */
493 pci_write_config8(ctrl.d0f3, 0x60, 0x01);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000494
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000495 /* Disable DRAM refresh */
496 pci_write_config8(ctrl.d0f3,0x6a,0x0);
497
498
499 /* Memory Pads Driving and Range Select */
500 pci_write_config8(ctrl.d0f3, 0xe2, 0xAA);
501 pci_write_config8(ctrl.d0f3, 0xe3, 0x00);
502 pci_write_config8(ctrl.d0f3, 0xe4, 0x99);
503
504 /* DRAM signal timing control */
Jon Harrison1825be22009-08-17 17:09:46 +0000505 pci_write_config8(ctrl.d0f3, 0x74, 0x99);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000506 pci_write_config8(ctrl.d0f3, 0x76, 0x09);
Jon Harrison1825be22009-08-17 17:09:46 +0000507 pci_write_config8(ctrl.d0f3, 0x77, 0x12);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000508
509 pci_write_config8(ctrl.d0f3, 0xe0, 0xAA);
510 pci_write_config8(ctrl.d0f3, 0xe1, 0x00);
511 pci_write_config8(ctrl.d0f3, 0xe6, 0x00);
512 pci_write_config8(ctrl.d0f3, 0xe8, 0xEE);
513 pci_write_config8(ctrl.d0f3, 0xea, 0xEE);
514
515
516 /* SPD byte 5 # of physical banks */
Uwe Hermannd773fd32010-11-20 20:23:08 +0000517 b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000518 c = b | 0x40;
519
520 pci_write_config8(ctrl.d0f3, 0xb0, c);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000521
Jon Harrison1825be22009-08-17 17:09:46 +0000522 /* Set RAM Decode method */
523 pci_write_config8(ctrl.d0f3, 0x55, 0x0a);
524
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000525 /* Enable DIMM Ranks */
526 pci_write_config8(ctrl.d0f3, 0x48, ma);
527 udelay(200);
528
Uwe Hermannd773fd32010-11-20 20:23:08 +0000529 c = smbus_read_byte(DIMM0, SPD_SUPPORTED_BURST_LENGTHS);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000530 c &= 0x08;
531 if ( c == 0x08 )
532 {
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000533 print_debug("Setting Burst Length 8\n");
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000534 /*
535 CPU Frequency Device 0 Function 2 Offset 54
536
537 CPU FSB Operating Frequency (bits 7:5)
538 000 : 100MHz 001 : 133MHz
Stefan Reinauer14e22772010-04-27 06:56:47 +0000539 010 : 200MHz
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000540 011->111 : Reserved
Stefan Reinauer14e22772010-04-27 06:56:47 +0000541
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000542 SDRAM BL8 (4)
Stefan Reinauer14e22772010-04-27 06:56:47 +0000543
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000544 Don't change Frequency from power up defaults
545 This seems to lockup the RAM interface
Stefan Reinauer14e22772010-04-27 06:56:47 +0000546 */
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000547 c = pci_read_config8(ctrl.d0f2, 0x54);
548 c |= 0x10;
549 pci_write_config8(ctrl.d0f2, 0x54, c);
550 i = 0x008; // Used later to set SDRAM MSR
551 }
552
Jon Harrison1825be22009-08-17 17:09:46 +0000553
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000554 for( bank = 0 , bank_address=0; bank <= b ; bank++) {
555/*
556 DDR init described in Via VT8623 BIOS Porting Guide. Pg 28 (4.2.3.1)
557*/
558
559 /* NOP command enable */
560 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
561 c &= 0xf8; /* Clear bits 2-0. */
562 c |= RAM_COMMAND_NOP;
Stefan Reinauer14e22772010-04-27 06:56:47 +0000563 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000564
565 /* read a double word from any address of the dimm */
566 dimm_read(bank_address,0x1f000);
567 //udelay(200);
568
569 /* All bank precharge Command Enable */
570 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
571 c &= 0xf8; /* Clear bits 2-0. */
572 c |= RAM_COMMAND_PRECHARGE;
Stefan Reinauer14e22772010-04-27 06:56:47 +0000573 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000574 dimm_read(bank_address,0x1f000);
575
576
577 /* MSR Enable Low DIMM*/
578 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
579 c &= 0xf8; /* Clear bits 2-0. */
580 c |= RAM_COMMAND_MSR_LOW;
Stefan Reinauer14e22772010-04-27 06:56:47 +0000581 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
582 /* TODO: Bank Addressing for Different Numbers of Row Addresses */
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000583 dimm_read(bank_address,0x2000);
584 udelay(1);
585 dimm_read(bank_address,0x800);
586 udelay(1);
587
588 /* All banks precharge Command Enable */
589 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
590 c &= 0xf8; /* Clear bits 2-0. */
591 c |= RAM_COMMAND_PRECHARGE;
Stefan Reinauer14e22772010-04-27 06:56:47 +0000592 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000593 dimm_read(bank_address,0x1f200);
594
595 /* CBR Cycle Enable */
596 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
597 c &= 0xf8; /* Clear bits 2-0. */
598 c |= RAM_COMMAND_CBR;
Stefan Reinauer14e22772010-04-27 06:56:47 +0000599 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000600
601 /* Read 8 times */
602 for (c=0;c<8;c++) {
603 dimm_read(bank_address,0x1f300);
604 udelay(100);
605 }
606
607 /* MSR Enable */
608 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
609 c &= 0xf8; /* Clear bits 2-0. */
610 c |= RAM_COMMAND_MSR_LOW;
Stefan Reinauer14e22772010-04-27 06:56:47 +0000611 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000612
613
Stefan Reinauer14e22772010-04-27 06:56:47 +0000614/*
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000615 Mode Register Definition
616 with adjustement so that address calculation is correct - 64 bit technology, therefore
617 a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
618 to DIMM as a row or column address.
619
620 MR[9-7] CAS Latency
621 MR[6] Burst Type 0 = sequential, 1 = interleaved
622 MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved
Stefan Reinauer14e22772010-04-27 06:56:47 +0000623 MR[0-2] dont care
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000624
Stefan Reinauer14e22772010-04-27 06:56:47 +0000625 CAS Latency
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000626 000 reserved
627 001 reserved
628 010 2
629 011 3
630 100 reserved
631 101 1.5
632 110 2.5
633 111 reserved
634
635 CAS 2 0101011000 = 0x158
636 CAS 2.5 1101011000 = 0x358
637 CAS 3 0111011000 = 0x1d8
638
639*/
640 c = pci_read_config8(ctrl.d0f3, 0x56);
641 if( (c & 0x30) == 0x10 )
642 dimm_read(bank_address,(0x150 + i));
643 else if((c & 0x30) == 0x20 )
644 dimm_read(bank_address,(0x350 + i));
645 else
646 dimm_read(bank_address,(0x1d0 + i));
647
648
649 /* Normal SDRAM Mode */
650 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
651 c &= 0xf8; /* Clear bits 2-0. */
652 c |= RAM_COMMAND_NORMAL;
653 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000654
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000655 bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000;
656 } // end of for each bank
657
Stefan Reinauer14e22772010-04-27 06:56:47 +0000658
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000659 /* Set DRAM DQS Output Control */
660 pci_write_config8(ctrl.d0f3, 0x79, 0x11);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000661
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000662 /* Set DQS A/B Input delay to defaults */
663 pci_write_config8(ctrl.d0f3, 0x7A, 0xA1);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000664 pci_write_config8(ctrl.d0f3, 0x7B, 0x62);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000665
Jon Harrison1825be22009-08-17 17:09:46 +0000666 /* DQS Duty Cycle Control */
667 pci_write_config8(ctrl.d0f3, 0xED, 0x11);
668
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000669 /* SPD byte 5 # of physical banks */
Uwe Hermannd773fd32010-11-20 20:23:08 +0000670 b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
Stefan Reinauer14e22772010-04-27 06:56:47 +0000671
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000672 /* determine low bond */
673 if( b == 2)
674 bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000;
675 else
676 bank_address = 0;
677
Jon Harrison1825be22009-08-17 17:09:46 +0000678 for(i = 0x30 ; i < 0x0ff; i++){
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000679 pci_write_config8(ctrl.d0f3,0x70,i);
680 // clear
681 *(volatile unsigned long*)(0x4000) = 0;
682 *(volatile unsigned long*)(0x4100+bank_address) = 0;
683 *(volatile unsigned long*)(0x4200) = 0;
684 *(volatile unsigned long*)(0x4300+bank_address) = 0;
685 *(volatile unsigned long*)(0x4400) = 0;
686 *(volatile unsigned long*)(0x4500+bank_address) = 0;
687
688 // fill
689 *(volatile unsigned long*)(0x4000) = 0x12345678;
690 *(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
691 *(volatile unsigned long*)(0x4200) = 0x78123456;
692 *(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
693 *(volatile unsigned long*)(0x4400) = 0x56781234;
694 *(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
695
696 // verify
697 if( *(volatile unsigned long*)(0x4000) != 0x12345678)
698 continue;
699
700 if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
701 continue;
702
703 if( *(volatile unsigned long*)(0x4200) != 0x78123456)
704 continue;
705
706 if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
707 continue;
708
709 if( *(volatile unsigned long*)(0x4400) != 0x56781234)
710 continue;
711
712 if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
713 continue;
714
715 // if everything verified then found low bond
716 break;
Stefan Reinauer14e22772010-04-27 06:56:47 +0000717
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000718 }
Stefan Reinauer14e22772010-04-27 06:56:47 +0000719 print_val("\nLow Bond ",i);
720 if( i < 0xff ){
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000721 c = i++;
722 for( ; i <0xff ; i++){
723 pci_write_config8(ctrl.d0f3,0x70, i);
724 // clear
725 *(volatile unsigned long*)(0x8000) = 0;
726 *(volatile unsigned long*)(0x8100+bank_address) = 0;
727 *(volatile unsigned long*)(0x8200) = 0x0;
728 *(volatile unsigned long*)(0x8300+bank_address) = 0;
729 *(volatile unsigned long*)(0x8400) = 0x0;
730 *(volatile unsigned long*)(0x8500+bank_address) = 0;
731
732 // fill
733 *(volatile unsigned long*)(0x8000) = 0x12345678;
734 *(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
735 *(volatile unsigned long*)(0x8200) = 0x78123456;
736 *(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
737 *(volatile unsigned long*)(0x8400) = 0x56781234;
738 *(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
739
740 // verify
741 if( *(volatile unsigned long*)(0x8000) != 0x12345678)
742 break;
743
744 if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
745 break;
746
747 if( *(volatile unsigned long*)(0x8200) != 0x78123456)
748 break;
749
750 if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
751 break;
752
753 if( *(volatile unsigned long*)(0x8400) != 0x56781234)
754 break;
755
756 if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
757 break;
758
759 }
760 print_val(" High Bond ",i);
761 c = ((i - c)<<1)/3 + c;
762 print_val(" Setting DQS delay",c);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000763 print_debug("\n");
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000764 pci_write_config8(ctrl.d0f3,0x70,c);
765 }else{
766 pci_write_config8(ctrl.d0f3,0x70,0x67);
767 }
768
Jon Harrison1825be22009-08-17 17:09:46 +0000769 /* Set DQS ChA Data Output Delay to the default */
770 pci_write_config8(ctrl.d0f3, 0x71, 0x65);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000771
Jon Harrison1825be22009-08-17 17:09:46 +0000772 /* Set Ch B DQS Output Delays */
773 pci_write_config8(ctrl.d0f3, 0x72, 0x2a);
774 pci_write_config8(ctrl.d0f3, 0x73, 0x29);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000775
Jon Harrison1825be22009-08-17 17:09:46 +0000776 pci_write_config8(ctrl.d0f3, 0x78, 0x03);
777
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000778 /* Mystery Value */
779 pci_write_config8(ctrl.d0f3, 0x67, 0x50);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000780
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000781 /* Enable Toggle Limiting */
782 pci_write_config8(ctrl.d0f4, 0xA3, 0x80);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000783
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000784/*
785 DRAM refresh rate Device 0 F3 Offset 6a
Stefan Reinauer14e22772010-04-27 06:56:47 +0000786 TODO :: Fix for different DRAM technologies
787 other than 512Mb and DRAM Freq
788 Units of 16 DRAM clock cycles - 1.
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000789*/
790 //c = pci_read_config8(ctrl.d0f3, 0x68);
791 //c &= 0x07;
Uwe Hermannd773fd32010-11-20 20:23:08 +0000792 //b = smbus_read_byte(DIMM0, SPD_REFRESH);
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000793 //print_val("SPD_REFRESH = ", b);
794
Jon Harrison1825be22009-08-17 17:09:46 +0000795 pci_write_config8(ctrl.d0f3,0x6a,0x65);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000796
Jon Harrison1825be22009-08-17 17:09:46 +0000797 /* SMM and APIC decoding, we do not use SMM */
798 b = 0x29;
799 pci_write_config8(ctrl.d0f3, 0x86, b);
800 /* SMM and APIC decoding mirror */
801 pci_write_config8(ctrl.d0f7, 0xe6, b);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000802
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000803 /* Open Up the Rest of the Shadow RAM */
804 pci_write_config8(ctrl.d0f3,0x80,0xff);
805 pci_write_config8(ctrl.d0f3,0x81,0xff);
806
807 /* pci */
808 pci_write_config8(ctrl.d0f7,0x70,0x82);
809 pci_write_config8(ctrl.d0f7,0x73,0x01);
810 pci_write_config8(ctrl.d0f7,0x76,0x50);
811
812 pci_write_config8(ctrl.d0f7,0x71,0xc8);
Stefan Reinauer14e22772010-04-27 06:56:47 +0000813
Jon Harrisoncfb9cd22009-07-01 10:57:25 +0000814
815 /* VGA device. */
816 pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
817 pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000818 print_debug("CN400 raminit.c done\n");
Stefan Reinauer14e22772010-04-27 06:56:47 +0000819}